3 Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved
5 This program and the accompanying materials are licensed and made available under
6 the terms and conditions of the BSD License that accompanies this distribution.
7 The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
19 Macros that simplify accessing PCH devices's PCI registers.
21 ** NOTE ** these macros assume the PCH device is on BUS 0
24 #ifndef _PCH_ACCESS_H_
25 #define _PCH_ACCESS_H_
28 #include "PchCommonDefinitions.h"
30 #ifndef STALL_ONE_MICRO_SECOND
31 #define STALL_ONE_MICRO_SECOND 1
33 #ifndef STALL_ONE_SECOND
34 #define STALL_ONE_SECOND 1000000
38 /// Memory Mapped PCI Access macros
41 /// PCI Device MM Base
44 #define MmPciAddress(Segment, Bus, Device, Function, Register) \
45 ((UINTN) PatchPcdGet64 (PcdPciExpressBaseAddress) + \
46 (UINTN) (Bus << 20) + \
47 (UINTN) (Device << 15) + \
48 (UINTN) (Function << 12) + \
53 /// Pch Controller PCI access macros
55 #define PCH_RCRB_BASE ( \
56 MmioRead32 (MmPciAddress (0, \
57 DEFAULT_PCI_BUS_NUMBER_PCH, \
58 PCI_DEVICE_NUMBER_PCH_LPC, \
59 PCI_FUNCTION_NUMBER_PCH_LPC), \
60 R_PCH_LPC_RCBA)) & B_PCH_LPC_RCBA_BAR \
64 /// Device 0x1b, Function 0
66 #define PchAzaliaPciCfg32(Register) \
69 DEFAULT_PCI_BUS_NUMBER_PCH, \
70 PCI_DEVICE_NUMBER_PCH_AZALIA, \
75 #define PchAzaliaPciCfg32Or(Register, OrData) \
78 DEFAULT_PCI_BUS_NUMBER_PCH, \
79 PCI_DEVICE_NUMBER_PCH_AZALIA, \
85 #define PchAzaliaPciCfg32And(Register, AndData) \
88 DEFAULT_PCI_BUS_NUMBER_PCH, \
89 PCI_DEVICE_NUMBER_PCH_AZALIA, \
95 #define PchAzaliaPciCfg32AndThenOr(Register, AndData, OrData) \
98 DEFAULT_PCI_BUS_NUMBER_PCH, \
99 PCI_DEVICE_NUMBER_PCH_AZALIA, \
105 #define PchAzaliaPciCfg16(Register) \
108 DEFAULT_PCI_BUS_NUMBER_PCH, \
109 PCI_DEVICE_NUMBER_PCH_AZALIA, \
114 #define PchAzaliaPciCfg16Or(Register, OrData) \
117 DEFAULT_PCI_BUS_NUMBER_PCH, \
118 PCI_DEVICE_NUMBER_PCH_AZALIA, \
124 #define PchAzaliaPciCfg16And(Register, AndData) \
127 DEFAULT_PCI_BUS_NUMBER_PCH, \
128 PCI_DEVICE_NUMBER_PCH_AZALIA, \
134 #define PchAzaliaPciCfg16AndThenOr(Register, AndData, OrData) \
137 DEFAULT_PCI_BUS_NUMBER_PCH, \
138 PCI_DEVICE_NUMBER_PCH_AZALIA, \
145 #define PchAzaliaPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_AZALIA, 0, Register))
147 #define PchAzaliaPciCfg8Or(Register, OrData) \
150 DEFAULT_PCI_BUS_NUMBER_PCH, \
151 PCI_DEVICE_NUMBER_PCH_AZALIA, \
157 #define PchAzaliaPciCfg8And(Register, AndData) \
160 DEFAULT_PCI_BUS_NUMBER_PCH, \
161 PCI_DEVICE_NUMBER_PCH_AZALIA, \
167 #define PchAzaliaPciCfg8AndThenOr(Register, AndData, OrData) \
170 DEFAULT_PCI_BUS_NUMBER_PCH, \
171 PCI_DEVICE_NUMBER_PCH_AZALIA, \
179 /// Device 0x1f, Function 0
181 #define PchLpcPciCfg32(Register) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))
183 #define PchLpcMmioOr32 (Register, OrData) \
186 DEFAULT_PCI_BUS_NUMBER_PCH, \
187 PCI_DEVICE_NUMBER_PCH_LPC, \
193 #define PchLpcPciCfg32And(Register, AndData) \
196 DEFAULT_PCI_BUS_NUMBER_PCH, \
197 PCI_DEVICE_NUMBER_PCH_LPC, \
203 #define PchLpcPciCfg32AndThenOr(Register, AndData, OrData) \
206 DEFAULT_PCI_BUS_NUMBER_PCH, \
207 PCI_DEVICE_NUMBER_PCH_LPC, \
214 #define PchLpcPciCfg16(Register) MmioRead16 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))
216 #define PchLpcPciCfg16Or(Register, OrData) \
219 DEFAULT_PCI_BUS_NUMBER_PCH, \
220 PCI_DEVICE_NUMBER_PCH_LPC, \
226 #define PchLpcPciCfg16And(Register, AndData) \
229 DEFAULT_PCI_BUS_NUMBER_PCH, \
230 PCI_DEVICE_NUMBER_PCH_LPC, \
236 #define PchLpcPciCfg16AndThenOr(Register, AndData, OrData) \
239 DEFAULT_PCI_BUS_NUMBER_PCH, \
240 PCI_DEVICE_NUMBER_PCH_LPC, \
247 #define PchLpcPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_LPC, 0, Register))
249 #define PchLpcPciCfg8Or(Register, OrData) \
252 DEFAULT_PCI_BUS_NUMBER_PCH, \
253 PCI_DEVICE_NUMBER_PCH_LPC, \
259 #define PchLpcPciCfg8And(Register, AndData) \
262 DEFAULT_PCI_BUS_NUMBER_PCH, \
263 PCI_DEVICE_NUMBER_PCH_LPC, \
269 #define PchLpcPciCfg8AndThenOr(Register, AndData, OrData) \
272 DEFAULT_PCI_BUS_NUMBER_PCH, \
273 PCI_DEVICE_NUMBER_PCH_LPC, \
282 /// SATA device 0x13, Function 0
284 #define PchSataPciCfg32(Register) MmioRead32 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))
286 #define PchSataPciCfg32Or(Register, OrData) \
289 DEFAULT_PCI_BUS_NUMBER_PCH, \
290 PCI_DEVICE_NUMBER_PCH_SATA, \
291 PCI_FUNCTION_NUMBER_PCH_SATA, \
296 #define PchSataPciCfg32And(Register, AndData) \
299 DEFAULT_PCI_BUS_NUMBER_PCH, \
300 PCI_DEVICE_NUMBER_PCH_SATA, \
301 PCI_FUNCTION_NUMBER_PCH_SATA, \
306 #define PchSataPciCfg32AndThenOr(Register, AndData, OrData) \
309 DEFAULT_PCI_BUS_NUMBER_PCH, \
310 PCI_DEVICE_NUMBER_PCH_SATA, \
311 PCI_FUNCTION_NUMBER_PCH_SATA, \
317 #define PchSataPciCfg16(Register) MmioRead16 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))
319 #define PchSataPciCfg16Or(Register, OrData) \
322 DEFAULT_PCI_BUS_NUMBER_PCH, \
323 PCI_DEVICE_NUMBER_PCH_SATA, \
324 PCI_FUNCTION_NUMBER_PCH_SATA, \
329 #define PchSataPciCfg16And(Register, AndData) \
332 DEFAULT_PCI_BUS_NUMBER_PCH, \
333 PCI_DEVICE_NUMBER_PCH_SATA, \
334 PCI_FUNCTION_NUMBER_PCH_SATA, \
339 #define PchSataPciCfg16AndThenOr(Register, AndData, OrData) \
342 DEFAULT_PCI_BUS_NUMBER_PCH, \
343 PCI_DEVICE_NUMBER_PCH_SATA, \
344 PCI_FUNCTION_NUMBER_PCH_SATA, \
350 #define PchSataPciCfg8(Register) MmioRead8 (MmPciAddress (0, DEFAULT_PCI_BUS_NUMBER_PCH, PCI_DEVICE_NUMBER_PCH_SATA, PCI_FUNCTION_NUMBER_PCH_SATA, Register))
352 #define PchSataPciCfg8Or(Register, OrData) \
355 DEFAULT_PCI_BUS_NUMBER_PCH, \
356 PCI_DEVICE_NUMBER_PCH_SATA, \
357 PCI_FUNCTION_NUMBER_PCH_SATA, \
362 #define PchSataPciCfg8And(Register, AndData) \
365 DEFAULT_PCI_BUS_NUMBER_PCH, \
366 PCI_DEVICE_NUMBER_PCH_SATA, \
367 PCI_FUNCTION_NUMBER_PCH_SATA, \
372 #define PchSataPciCfg8AndThenOr(Register, AndData, OrData) \
375 DEFAULT_PCI_BUS_NUMBER_PCH, \
376 PCI_DEVICE_NUMBER_PCH_SATA, \
377 PCI_FUNCTION_NUMBER_PCH_SATA, \
385 /// Root Complex Register Block
387 #define PchMmRcrb32(Register) MmioRead32 (PCH_RCRB_BASE + Register)
389 #define PchMmRcrb32Or(Register, OrData) MmioOr32 (PCH_RCRB_BASE + Register, OrData)
391 #define PchMmRcrb32And(Register, AndData) MmioAnd32 (PCH_RCRB_BASE + Register, AndData)
393 #define PchMmRcrb32AndThenOr(Register, AndData, OrData) MmioAndThenOr32 (PCH_RCRB_BASE + Register, AndData, OrData)
395 #define PchMmRcrb16(Register) MmioRead16 (PCH_RCRB_BASE + Register)
397 #define PchMmRcrb16Or(Register, OrData) MmioOr16 (PCH_RCRB_BASE + Register, OrData)
399 #define PchMmRcrb16And(Register, AndData) MmioAnd16 (PCH_RCRB_BASE + Register, AndData)
401 #define PchMmRcrb16AndThenOr(Register, AndData, OrData) MmioAndThenOr16 (PCH_RCRB_BASE + Register, AndData, OrData)
403 #define PchMmRcrb8(Register) MmioRead8 (PCH_RCRB_BASE + Register)
405 #define PchMmRcrb8Or(Register, OrData) MmioOr8 (PCH_RCRB_BASE + Register, OrData)
407 #define PchMmRcrb8And(Register, AndData) MmioAnd8 (PCH_RCRB_BASE + Register, AndData)
409 #define PchMmRcrb8AndThenOr(Register, AndData, OrData) MmioAndThenOr8 (PCH_RCRB_BASE + Register, AndData, OrData)
417 /// Message Bus Registers
419 #define MC_MCR 0x000000D0 // Cunit Message Control Register
420 #define MC_MDR 0x000000D4 // Cunit Message Data Register
421 #define MC_MCRX 0x000000D8 // Cunit Message Control Register Extension
426 #define MSG_BUS_ENABLED 0x000000F0
427 #define MSGBUS_MASKHI 0xFFFFFF00
428 #define MSGBUS_MASKLO 0x000000FF
429 #define MESSAGE_DWORD_EN BIT4 | BIT5 | BIT6 | BIT7
431 #define PchMsgBusRead32(PortId, Register, Dbuff, ReadOpCode, WriteOpCode) \
433 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
434 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
435 (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
438 #define PchMsgBusAnd32(PortId, Register, Dbuff, AndData, ReadOpCode, WriteOpCode) \
440 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
441 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
442 (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
443 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
444 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) (Dbuff & AndData)); \
445 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
448 #define PchMsgBusOr32(PortId, Register, Dbuff, OrData, ReadOpCode, WriteOpCode) \
450 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
451 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
452 (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
453 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
454 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) (Dbuff | OrData)); \
455 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
458 #define PchMsgBusAndThenOr32(PortId, Register, Dbuff, AndData, OrData, ReadOpCode, WriteOpCode) \
460 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
461 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((ReadOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
462 (Dbuff) = MmioRead32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR)); \
463 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCRX), (UINT32) (Register & MSGBUS_MASKHI)); \
464 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MDR ), (UINT32) ((Dbuff & AndData) | OrData)); \
465 MmioWrite32 ((UINTN) (PatchPcdGet64 (PcdPciExpressBaseAddress) + MC_MCR ), (UINT32) ((WriteOpCode << 24) | (PortId << 16) | ((Register & MSGBUS_MASKLO) << 8) | MESSAGE_DWORD_EN)); \
468 typedef struct _PCH_MSG_BUS_TABLE_STRUCT
{
475 } PCH_MSG_BUS_TABLE_STRUCT_TABLE_STRUCT
;