Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/Protocol/PchPlatformPolicy.h

   1 /**
   2 **/
   3 /**
   4
   5 Copyright (c) 2013  - 2014, Intel Corporation. All rights reserved
   6
   7   This program and the accompanying materials are licensed and made available under
   8   the terms and conditions of the BSD License that accompanies this distribution.
   9   The full text of the license may be found at
  10   http://opensource.org/licenses/bsd-license.php.
  11
  12   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14
  15
  16
  17   @file
  18   PchPlatformPolicy.h
  19
  20   @brief
  21   PCH policy protocol produced by a platform driver specifying various
  22   expected PCH settings. This protocol is consumed by the PCH drivers.
  23
  24 **/
  25 #ifndef _PCH_PLATFORM_POLICY_H_
  26 #define _PCH_PLATFORM_POLICY_H_
  27
  28
  29 //
  30 #include "PchRegs.h"
  31 #ifndef ECP_FLAG
  32 #include "Uefi.h"
  33 #endif
  34
  35 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_GUID \
  36   { \
  37     0x4b0165a9, 0x61d6, 0x4e23, 0xa0, 0xb5, 0x3e, 0xc7, 0x9c, 0x2e, 0x30, 0xd5 \
  38   }
  39 extern EFI_GUID                                   gDxePchPlatformPolicyProtocolGuid;
  40
  41 ///
  42 /// Forward reference for ANSI C compatibility
  43 ///
  44 typedef struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL  DXE_PCH_PLATFORM_POLICY_PROTOCOL;
  45
  46 ///
  47 /// Protocol revision number
  48 /// Any backwards compatible changes to this protocol will result in an update in the revision number
  49 /// Major changes will require publication of a new protocol
  50 ///
  51 /// Revision 1: Original version
  52 ///
  53 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_1 1
  54 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_2 2
  55 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_3 3
  56 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_4 4
  57 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_5 5
  58 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_6 6
  59 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_7 7
  60 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_8 8
  61 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_9 9
  62 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_10 10
  63 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_11 11
  64 #define DXE_PCH_PLATFORM_POLICY_PROTOCOL_REVISION_12 12
  65
  66 ///
  67 /// Generic definitions for device enabling/disabling used by PCH code.
  68 ///
  69 #define PCH_DEVICE_ENABLE   1
  70 #define PCH_DEVICE_DISABLE  0
  71
  72 ///
  73 /// ---------------------------- Device Enabling ------------------------------
  74 ///
  75 /// PCH Device enablings
  76 ///
  77 typedef struct {
  78   UINT8 Lan               : 1;    /// 0: Disable; 1: Enable
  79   UINT8 Azalia            : 2;    /// 0: Disable; 1: Enable; 2: Auto
  80   UINT8 Sata              : 1;    /// 0: Disable; 1: Enable
  81   UINT8 Smbus             : 1;    /// 0: Disable; 1: Enable
  82   UINT8 LpeEnabled        : 2;    /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
  83   UINT8 Reserved[1];              /// Reserved fields for future expansion w/o protocol change
  84 } PCH_DEVICE_ENABLING;
  85
  86 ///
  87 /// ---------------------------- USB Config -----------------------------
  88 ///
  89 ///
  90 /// Overcurrent pins
  91 ///
  92 typedef enum {
  93   PchUsbOverCurrentPin0 = 0,
  94   PchUsbOverCurrentPin1,
  95   PchUsbOverCurrentPin2,
  96   PchUsbOverCurrentPin3,
  97   PchUsbOverCurrentPin4,
  98   PchUsbOverCurrentPin5,
  99   PchUsbOverCurrentPin6,
 100   PchUsbOverCurrentPin7,
 101   PchUsbOverCurrentPinSkip,
 102   PchUsbOverCurrentPinMax
 103 } PCH_USB_OVERCURRENT_PIN;
 104
 105 typedef struct {
 106   UINT8   Enable            : 1;    /// 0: Disable; 1: Enable. This would take effect while UsbPerPortCtl is enabled
 107   UINT8   Panel             : 1;    /// 0: Back Panel Port; 1: Front Panel Port.
 108   UINT8   Dock              : 1;    /// 0: Not docking port; 1: Docking Port.
 109   UINT8   Rsvdbits          : 5;
 110 } PCH_USB_PORT_SETTINGS;
 111
 112 typedef struct {
 113   UINT8 Enable              : 1;    /// 0: Disable; 1: Enable
 114   UINT8 Rsvdbits            : 7;
 115 } PCH_USB20_CONTROLLER_SETTINGS;
 116
 117 typedef struct {
 118   UINT8 Enable              : 2;    /// 0: 0: Disabled; 1: PCI Mode 2: ACPI Mode
 119   UINT8 Rsvdbits            : 6;
 120 } PCH_USBOTG_CONTROLLER_SETTINGS;
 121
 122 #define PCH_XHCI_MODE_OFF         0
 123 #define PCH_XHCI_MODE_ON          1
 124 #define PCH_XHCI_MODE_AUTO        2
 125 #define PCH_XHCI_MODE_SMARTAUTO   3
 126
 127 #define PCH_EHCI_DEBUG_OFF        0
 128 #define PCH_EHCI_DEBUG_ON         1
 129
 130 #define PCH_USB_FRONT_PANEL       1
 131 #define PCH_USB_BACK_PANEL        0
 132
 133 typedef struct {
 134   UINT8 Mode               : 2;    /// 0: Disable; 1: Enable, 2: Auto, 3: Smart Auto
 135   UINT8 PreBootSupport     : 1;    /// 0: No xHCI driver available; 1: xHCI driver available
 136   UINT8 XhciStreams        : 1;    /// 0: Disable; 1: Enable
 137   UINT8 Rsvdbits           : 4;
 138 } PCH_USB30_CONTROLLER_SETTINGS;
 139
 140 typedef struct {
 141   UINT8 UsbPerPortCtl       : 1;    /// 0: Disable; 1: Enable Per-port enable control
 142   UINT8 Ehci1Usbr           : 1;    /// 0: Disable; 1: Enable EHCI 1 USBR
 143   UINT8 RsvdBits            : 6;
 144   PCH_USB_PORT_SETTINGS          PortSettings[PCH_USB_MAX_PHYSICAL_PORTS];
 145   PCH_USB20_CONTROLLER_SETTINGS  Usb20Settings[PchEhciControllerMax];
 146   PCH_USB30_CONTROLLER_SETTINGS  Usb30Settings;
 147   PCH_USBOTG_CONTROLLER_SETTINGS UsbOtgSettings;
 148   PCH_USB_OVERCURRENT_PIN        Usb20OverCurrentPins[PCH_USB_MAX_PHYSICAL_PORTS];
 149   PCH_USB_OVERCURRENT_PIN        Usb30OverCurrentPins[PCH_XHCI_MAX_USB3_PORTS];
 150   ///
 151   /// The length of Usb Port to configure the USB transmitter,
 152   /// Bits [16:4] represents length of Usb Port in inches using octal format and [3:0] is for the decimal Point.
 153   ///
 154   UINT16                        Usb20PortLength[PCH_EHCI_MAX_PORTS];
 155   UINT16                        EhciDebug;
 156   UINT16                        UsbXhciLpmSupport;
 157
 158 } PCH_USB_CONFIG;
 159
 160 ///
 161 /// ---------------------------- PCI Express Config ----------------------
 162 ///
 163 /// The values before AutoConfig match the setting of PCI Express Base Specification 1.1, please be careful for adding new feature
 164 ///
 165 typedef enum {
 166   PchPcieAspmDisabled,
 167   PchPcieAspmL0s,
 168   PchPcieAspmL1,
 169   PchPcieAspmL0sL1,
 170   PchPcieAspmAutoConfig,
 171   PchPcieAspmMax
 172 } PCH_PCI_EXPRESS_ASPM_CONTROL;
 173
 174 ///
 175 /// Refer to PCH EDS for the PCH implementation values corresponding
 176 /// to below PCI-E spec defined ranges
 177 ///
 178 typedef enum {
 179   PchPciECompletionTO_Default,
 180   PchPciECompletionTO_50_100us,
 181   PchPciECompletionTO_1_10ms,
 182   PchPciECompletionTO_16_55ms,
 183   PchPciECompletionTO_65_210ms,
 184   PchPciECompletionTO_260_900ms,
 185   PchPciECompletionTO_1_3P5s,
 186   PchPciECompletionTO_4_13s,
 187   PchPciECompletionTO_17_64s,
 188   PchPciECompletionTO_Disabled
 189 } PCH_PCIE_COMPLETION_TIMEOUT;
 190
 191 typedef struct {
 192   UINT8 Enable                          : 1;    /// Root Port enabling, 0: Disable; 1: Enable.
 193   UINT8 Hide                            : 1;    /// Whether or not to hide the configuration space of this port
 194   UINT8 SlotImplemented                 : 1;
 195   UINT8 HotPlug                         : 1;
 196   UINT8 PmSci                           : 1;
 197   UINT8 ExtSync                         : 1;    /// Extended Synch
 198   UINT8 Rsvdbits                        : 2;
 199   ///
 200   /// Error handlings
 201   ///
 202   UINT8 UnsupportedRequestReport        : 1;
 203   UINT8 FatalErrorReport                : 1;
 204   UINT8 NoFatalErrorReport              : 1;
 205   UINT8 CorrectableErrorReport          : 1;
 206   UINT8 PmeInterrupt                    : 1;
 207   UINT8 SystemErrorOnFatalError         : 1;
 208   UINT8 SystemErrorOnNonFatalError      : 1;
 209   UINT8 SystemErrorOnCorrectableError   : 1;
 210
 211   UINT8 AdvancedErrorReporting          : 1;
 212   UINT8 TransmitterHalfSwing            : 1;
 213   UINT8 Reserved                        : 6;    /// Reserved fields for future expansion w/o protocol change
 214
 215   UINT8 FunctionNumber;                         /// The function number this root port is mapped to.
 216   UINT8 PhysicalSlotNumber;
 217   PCH_PCIE_COMPLETION_TIMEOUT   CompletionTimeout;
 218   PCH_PCI_EXPRESS_ASPM_CONTROL  Aspm;
 219 } PCH_PCI_EXPRESS_ROOT_PORT_CONFIG;
 220
 221 typedef struct {
 222   /**
 223     VendorId
 224
 225       The vendor Id of Pci Express card ASPM setting override, 0xFFFF means any Vendor ID
 226
 227     DeviceId
 228
 229       The Device Id of Pci Express card ASPM setting override, 0xFFFF means any Device ID
 230
 231     RevId
 232
 233       The Rev Id of Pci Express card ASPM setting override, 0xFF means all steppings
 234
 235     BaseClassCode
 236
 237       The Base Class Code of Pci Express card ASPM setting override, 0xFF means all base class
 238
 239     SubClassCode
 240
 241       The Sub Class Code of Pci Express card ASPM setting override, 0xFF means all sub class
 242
 243
 244     EndPointAspm
 245
 246       The override ASPM setting from End point
 247   **/
 248   UINT16                        VendorId;
 249   UINT16                        DeviceId;
 250   UINT8                         RevId;
 251   UINT8                         BaseClassCode;
 252   UINT8                         SubClassCode;
 253   PCH_PCI_EXPRESS_ASPM_CONTROL  EndPointAspm;
 254 } PCH_PCIE_DEVICE_ASPM_OVERRIDE;
 255
 256 typedef struct {
 257   UINT16  VendorId; ///< PCI configuration space offset 0
 258   UINT16  DeviceId; ///< PCI configuration space offset 2
 259   UINT8   RevId;    ///< PCI configuration space offset 8; 0xFF means all steppings
 260   /**
 261     SnoopLatency bit definition
 262     Note: All Reserved bits must be set to 0
 263
 264     BIT[15]     - When set to 1b, indicates that the values in bits 9:0 are valid
 265                   When clear values in bits 9:0 will be ignored
 266     BITS[14:13] - Reserved
 267     BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
 268                   000b - 1 ns
 269                   001b - 32 ns
 270                   010b - 1024 ns
 271                   011b - 32,768 ns
 272                   100b - 1,048,576 ns
 273                   101b - 33,554,432 ns
 274                   110b - Reserved
 275                   111b - Reserved
 276     BITS[9:0]   - Snoop Latency Value. The value in these bits will be multiplied with
 277                   the scale in bits 12:10
 278   **/
 279   UINT16  SnoopLatency;
 280   /**
 281     NonSnoopLatency bit definition
 282     Note: All Reserved bits must be set to 0
 283
 284     BIT[15]     - When set to 1b, indicates that the values in bits 9:0 are valid
 285                   When clear values in bits 9:0 will be ignored
 286     BITS[14:13] - Reserved
 287     BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in these bits
 288                   000b - 1 ns
 289                   001b - 32 ns
 290                   010b - 1024 ns
 291                   011b - 32,768 ns
 292                   100b - 1,048,576 ns
 293                   101b - 33,554,432 ns
 294                   110b - Reserved
 295                   111b - Reserved
 296     BITS[9:0]   - Non Snoop Latency Value. The value in these bits will be multiplied with
 297                   the scale in bits 12:10
 298   **/
 299   UINT16  NonSnoopLatency;
 300 } PCH_PCIE_DEVICE_LTR_OVERRIDE;
 301
 302 typedef struct {
 303   ///
 304   /// Temp Bus Number range available to be assigned to
 305   /// each root port and its downstream devices for initialization
 306   /// of these devices before PCI Bus enumeration
 307   ///
 308   UINT8                             TempRootPortBusNumMin;
 309   UINT8                             TempRootPortBusNumMax;
 310   PCH_PCI_EXPRESS_ROOT_PORT_CONFIG  RootPort[PCH_PCIE_MAX_ROOT_PORTS];
 311   BOOLEAN                           RootPortClockGating;
 312   UINT8                             NumOfDevAspmOverride;     /// Number of PCI Express card Aspm setting override
 313   PCH_PCIE_DEVICE_ASPM_OVERRIDE     *DevAspmOverride;         /// The Pointer which is point to Pci Express card Aspm setting override
 314   UINT8                             PcieDynamicGating;        /// Need PMC enable it first from PMC 0x3_12 MCU 318.
 315 } PCH_PCI_EXPRESS_CONFIG;
 316
 317
 318 ///
 319 /// ---------------------------- SATA Config -----------------------------
 320 ///
 321 typedef enum {
 322   PchSataSpeedSupportGen1 = 1,
 323   PchSataSpeedSupportGen2
 324 } PCH_SATA_SPEED_SUPPORT;
 325
 326 typedef struct {
 327   UINT8 Enable          : 1;    /// 0: Disable; 1: Enable
 328   UINT8 HotPlug         : 1;    /// 0: Disable; 1: Enable
 329   UINT8 MechSw          : 1;    /// 0: Disable; 1: Enable
 330   UINT8 External        : 1;    /// 0: Disable; 1: Enable
 331   UINT8 SpinUp          : 1;    /// 0: Disable; 1: Enable the COMRESET initialization Sequence to the device
 332   UINT8 Rsvdbits        : 3;    /// Reserved fields for future expansion w/o protocol change
 333 } PCH_SATA_PORT_SETTINGS;
 334
 335 typedef struct {
 336   PCH_SATA_PORT_SETTINGS  PortSettings[PCH_AHCI_MAX_PORTS];
 337   UINT8 RaidAlternateId : 1;    /// 0: Disable; 1: Enable
 338   UINT8 Raid0           : 1;    /// 0: Disable; 1: Enable RAID0
 339   UINT8 Raid1           : 1;    /// 0: Disable; 1: Enable RAID1
 340   UINT8 Raid10          : 1;    /// 0: Disable; 1: Enable RAID10
 341   UINT8 Raid5           : 1;    /// 0: Disable; 1: Enable RAID5
 342   UINT8 Irrt            : 1;    /// 0: Disable; 1: Enable Intel Rapid Recovery Technology
 343   UINT8 OromUiBanner    : 1;    /// 0: Disable; 1: Enable OROM UI and BANNER
 344   UINT8 HddUnlock       : 1;    /// 0: Disable; 1: Indicates that the HDD password unlock in the OS is enabled
 345
 346   UINT8 LedLocate       : 1;    /// 0: Disable; 1: Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS
 347   UINT8 IrrtOnly        : 1;    /// 0: Disable; 1: Allow only IRRT drives to span internal and external ports
 348   UINT8 TestMode        : 1;    /// 0: Disable; 1: Allow entrance to the PCH SATA test modes
 349   UINT8 SalpSupport     : 1;    /// 0: Disable; 1: Enable Aggressive Link Power Management
 350   UINT8 LegacyMode      : 1;    /// 0: Native PCI mode; 1: Legacy mode, when SATA controller is operating in IDE mode
 351   UINT8 SpeedSupport    : 4;    /// Indicates the maximum speed the SATA controller can support
 352   /// 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2)
 353
 354   UINT8 Rsvdbits        : 7;    // Reserved fields for future expansion w/o protocol change
 355 } PCH_SATA_CONFIG;
 356 ///
 357 /// --------------------------- AZALIA Config ------------------------------
 358 ///
 359 typedef struct {
 360   UINT32  VendorDeviceId;
 361   UINT16  SubSystemId;
 362   UINT8   RevisionId;                       /// 0xFF applies to all steppings
 363   UINT8   FrontPanelSupport;
 364   UINT16  NumberOfRearJacks;
 365   UINT16  NumberOfFrontJacks;
 366 } PCH_AZALIA_VERB_TABLE_HEADER;
 367
 368 typedef struct {
 369   PCH_AZALIA_VERB_TABLE_HEADER  VerbTableHeader;
 370   UINT32                        *VerbTableData;
 371 } PCH_AZALIA_VERB_TABLE;
 372
 373 typedef struct {
 374   UINT8                 Pme       : 1;      /// 0: Disable; 1: Enable
 375   UINT8                 DS        : 1;      /// 0: Docking is not supported; 1:Docking is supported
 376   UINT8                 DA        : 1;      /// 0: Docking is not attached; 1:Docking is attached
 377   UINT8                 HdmiCodec : 1;      /// 0: Disable; 1: Enable
 378   UINT8                 AzaliaVCi : 1;      /// 0: Disable; 1: Enable
 379   UINT8                 Rsvdbits  : 3;
 380   UINT8                 AzaliaVerbTableNum; /// Number of verb tables provided by platform
 381   PCH_AZALIA_VERB_TABLE *AzaliaVerbTable;   /// Pointer to the actual verb table(s)
 382   UINT16                ResetWaitTimer;     /// The delay timer after Azalia reset, the value is number of microseconds
 383 } PCH_AZALIA_CONFIG;
 384
 385 ///
 386 /// --------------------------- Smbus Config ------------------------------
 387 ///
 388 typedef struct {
 389   UINT8 NumRsvdSmbusAddresses;
 390   UINT8 *RsvdSmbusAddressTable;
 391 } PCH_SMBUS_CONFIG;
 392
 393 ///
 394 /// --------------------------- Miscellaneous PM Config ------------------------------
 395 ///
 396 typedef struct {
 397   UINT8 MeWakeSts           : 1;
 398   UINT8 MeHrstColdSts       : 1;
 399   UINT8 MeHrstWarmSts       : 1;
 400   UINT8 MeHostPowerDn       : 1;
 401   UINT8 WolOvrWkSts         : 1;
 402   UINT8 Rsvdbits            : 3;
 403 } PCH_POWER_RESET_STATUS;
 404
 405 typedef struct {
 406   UINT8  PmeB0S5Dis         : 1;
 407   UINT8  WolEnableOverride  : 1;
 408   UINT8  Rsvdbits           : 6;
 409 } PCH_WAKE_CONFIG;
 410
 411 typedef enum {
 412   PchSlpS360us,
 413   PchSlpS31ms,
 414   PchSlpS350ms,
 415   PchSlpS32s
 416 } PCH_SLP_S3_MIN_ASSERT;
 417
 418 typedef enum {
 419   PchSlpS4PchTime,   /// The time defined in EDS Power Sequencing and Reset Signal Timings table
 420   PchSlpS41s,
 421   PchSlpS42s,
 422   PchSlpS43s,
 423   PchSlpS44s
 424 } PCH_SLP_S4_MIN_ASSERT;
 425
 426 typedef struct {
 427   ///
 428   /// Specify which Power/Reset bits need to be cleared by
 429   /// the PCH Init Driver.
 430   /// Usually platform drivers take care of these bits, but if
 431   /// not, let PCH Init driver clear the bits.
 432   ///
 433   PCH_POWER_RESET_STATUS  PowerResetStatusClear;
 434   ///
 435   /// Specify Wake Policy
 436   ///
 437   PCH_WAKE_CONFIG         WakeConfig;
 438   ///
 439   /// SLP_XX Minimum Assertion Width Policy
 440   ///
 441   PCH_SLP_S3_MIN_ASSERT   PchSlpS3MinAssert;
 442   PCH_SLP_S4_MIN_ASSERT   PchSlpS4MinAssert;
 443   UINT8                   SlpStrchSusUp : 1;  /// Enable/Disable SLP_X Stretching After SUS Well Power Up
 444   UINT8                   SlpLanLowDc   : 1;
 445   UINT8                   Rsvdbits      : 6;
 446 } PCH_MISC_PM_CONFIG;
 447
 448 ///
 449 /// --------------------------- Subsystem Vendor ID / Subsystem ID Config -----
 450 ///
 451 typedef struct {
 452   UINT16  SubSystemVendorId;
 453   UINT16  SubSystemId;
 454 } PCH_DEFAULT_SVID_SID;
 455
 456 ///
 457 /// --------------------------- Lock Down Config ------------------------------
 458 ///
 459 typedef struct {
 460   UINT8  GlobalSmi      : 1;
 461   UINT8  BiosInterface  : 1;
 462   UINT8  RtcLock        : 1;
 463   UINT8  BiosLock       : 1;
 464   UINT8  Rsvdbits       : 4;
 465   UINT8  PchBiosLockSwSmiNumber;
 466 } PCH_LOCK_DOWN_CONFIG;
 467 //
 468 // --------------------------- Serial IRQ Config ------------------------------
 469 //
 470 typedef enum {
 471   PchQuietMode,
 472   PchContinuousMode
 473 } PCH_SIRQ_MODE;
 474 ///
 475 /// Refer to SoC EDS for the details of Start Frame Pulse Width in Continuous and Quiet mode
 476 ///
 477
 478 typedef struct {
 479   BOOLEAN                 SirqEnable;       /// Determines if enable Serial IRQ
 480   PCH_SIRQ_MODE           SirqMode;         /// Serial IRQ Mode Select
 481 } PCH_LPC_SIRQ_CONFIG;
 482
 483 ///
 484 /// --------------------------- Power Optimizer Config ------------------------------
 485 ///
 486 typedef struct {
 487   UINT8  NumOfDevLtrOverride;                            /// Number of Pci Express card listed in LTR override table
 488   PCH_PCIE_DEVICE_LTR_OVERRIDE *DevLtrOverride;          /// Pointer to Pci Express devices LTR override table
 489 } PCH_PWR_OPT_CONFIG;
 490
 491 ///
 492 /// --------------------- Low Power Input Output Config ------------------------
 493 ///
 494 typedef struct {
 495   UINT8                   LpssPciModeEnabled    : 1;    /// Determines if LPSS PCI Mode enabled
 496   UINT8                   Dma0Enabled           : 1;     /// Determines if LPSS DMA1 enabled
 497   UINT8                   Dma1Enabled           : 1;     /// Determines if LPSS DMA2 enabled
 498   UINT8                   I2C0Enabled           : 1;     /// Determines if LPSS I2C #1 enabled
 499   UINT8                   I2C1Enabled           : 1;     /// Determines if LPSS I2C #2 enabled
 500   UINT8                   I2C2Enabled           : 1;     /// Determines if LPSS I2C #3 enabled
 501   UINT8                   I2C3Enabled           : 1;     /// Determines if LPSS I2C #4 enabled
 502   UINT8                   I2C4Enabled           : 1;     /// Determines if LPSS I2C #5 enabled
 503   UINT8                   I2C5Enabled           : 1;     /// Determines if LPSS I2C #6 enabled
 504   UINT8                   I2C6Enabled           : 1;     /// Determines if LPSS I2C #7 enabled
 505   UINT8                   Pwm0Enabled           : 1;     /// Determines if LPSS PWM #1 enabled
 506   UINT8                   Pwm1Enabled           : 1;     /// Determines if LPSS PWM #2 enabled
 507   UINT8                   Hsuart0Enabled        : 1;     /// Determines if LPSS HSUART #1 enabled
 508   UINT8                   Hsuart1Enabled        : 1;     /// Determines if LPSS HSUART #2 enabled
 509   UINT8                   SpiEnabled            : 1;     /// Determines if LPSS SPI enabled
 510   UINT8                   Rsvdbits              : 2;
 511 } PCH_LPSS_CONFIG;
 512
 513 ///
 514 /// ----------------------------- SCC Config --------------------------------
 515 ///
 516 typedef struct {
 517   UINT8                   eMMCEnabled           : 1;      /// Determines if SCC eMMC enabled
 518   UINT8                   SdioEnabled           : 1;      /// Determines if SCC SDIO enabled
 519   UINT8                   SdcardEnabled         : 1;      /// Determines if SCC SD Card enabled
 520   UINT8                   HsiEnabled            : 1;      /// Determines if SCC HSI enabled
 521   UINT8                   eMMC45Enabled         : 1;      /// Determines if SCC eMMC 4.5 enabled
 522   UINT8                   eMMC45DDR50Enabled    : 1;  /// Determines if DDR50 enabled for eMMC 4.5
 523   UINT8                   eMMC45HS200Enabled    : 1;  /// Determines if HS200nabled for eMMC 4.5
 524   UINT8                   Rsvdbits              : 1;
 525   UINT8                   SdCardSDR25Enabled    : 1;    /// Determines if SDR25 for SD Card
 526   UINT8                   SdCardDDR50Enabled    : 1;    /// Determines if DDR50 for SD Card
 527   UINT8                   Rsvdbits1             : 6;
 528   UINT8                   eMMC45RetuneTimerValue;  /// Determines retune timer value.
 529 } PCH_SCC_CONFIG;
 530
 531 ///
 532 /// ------------ General PCH Platform Policy protocol definition ------------
 533 ///
 534 struct _DXE_PCH_PLATFORM_POLICY_PROTOCOL {
 535   UINT8                   Revision;
 536   UINT8                   BusNumber;  /// PCI Bus Number of the PCH device
 537   PCH_DEVICE_ENABLING     *DeviceEnabling;
 538   PCH_USB_CONFIG          *UsbConfig;
 539   PCH_PCI_EXPRESS_CONFIG  *PciExpressConfig;
 540
 541   PCH_SATA_CONFIG         *SataConfig;
 542   PCH_AZALIA_CONFIG       *AzaliaConfig;
 543   PCH_SMBUS_CONFIG        *SmbusConfig;
 544   PCH_MISC_PM_CONFIG      *MiscPmConfig;
 545   PCH_DEFAULT_SVID_SID    *DefaultSvidSid;
 546   PCH_LOCK_DOWN_CONFIG    *LockDownConfig;
 547   PCH_LPC_SIRQ_CONFIG     *SerialIrqConfig;
 548   PCH_PWR_OPT_CONFIG      *PwrOptConfig;
 549   PCH_LPSS_CONFIG         *LpssConfig;
 550   PCH_SCC_CONFIG          *SccConfig;
 551   UINT8                   IdleReserve;
 552   UINT8                   EhciPllCfgEnable;
 553   UINT8                   AcpiHWRed; //Hardware Reduced Mode
 554 };
 555
 556 #endif