3 Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials are licensed and made available under
6 the terms and conditions of the BSD License that accompanies this distribution.
7 The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php.
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
21 Worker functions for PostCode
25 #include "EfiStatusCode.h"
29 EFI_STATUS_CODE_VALUE StatusValue
;
31 } EFI_STATUS_CODE_TO_PORT_80
;
35 // see Edk\Foundation\Library\EfiCommonLib\PostCode.c for DXE/BDS POST codes.
37 EFI_STATUS_CODE_TO_PORT_80 mPeiPort80Table
[] = {
41 {EFI_COMPUTING_UNIT_CHIPSET
| EFI_CU_PLATFORM_PEI_INIT
, 0x11},
42 {EFI_COMPUTING_UNIT_CHIPSET
| EFI_CU_PLATFORM_PEI_STEP1
, 0x12},
43 {EFI_COMPUTING_UNIT_CHIPSET
| EFI_CU_PLATFORM_PEI_STEP2
, 0x13},
44 {EFI_COMPUTING_UNIT_CHIPSET
| EFI_CU_PLATFORM_PEI_STEP3
, 0x14},
45 {EFI_COMPUTING_UNIT_CHIPSET
| EFI_CU_PLATFORM_PEI_STEP4
, 0x15},
50 {EFI_COMPUTING_UNIT_CHIPSET
| EFI_CU_SMBUS_PEI_INIT
, 0x16},
51 {EFI_COMPUTING_UNIT_CHIPSET
| EFI_CU_SMBUS_PEI_EXEC_ENTRY
, 0x17},
52 {EFI_COMPUTING_UNIT_CHIPSET
| EFI_CU_SMBUS_PEI_EXEC_EXIT
, 0x18},
57 {EFI_COMPUTING_UNIT_CHIPSET
| EFI_CU_CLOCK_PEI_INIT_ENTRY
, 0x19},
58 {EFI_COMPUTING_UNIT_CHIPSET
| EFI_CU_CLOCK_PEI_INIT_EXIT
, 0x1A},
61 // Over clocking support
63 {EFI_COMPUTING_UNIT_CHIPSET
| EFI_CU_OVERCLOCK_PEI_INIT_ENTRY
, 0x1B},
64 {EFI_COMPUTING_UNIT_CHIPSET
| EFI_CU_OVERCLOCK_PEI_INIT_EXIT
, 0x1C},
69 {EFI_COMPUTING_UNIT_MEMORY
| EFI_CU_MEMORY_PC_INIT_BEGIN
, 0x21},
70 {EFI_COMPUTING_UNIT_MEMORY
| EFI_CU_MEMORY_PC_SPD_READ
, 0x23},
71 {EFI_COMPUTING_UNIT_MEMORY
| EFI_CU_MEMORY_PC_PRESENCE_DETECT
, 0x24},
72 {EFI_COMPUTING_UNIT_MEMORY
| EFI_CU_MEMORY_PC_TIMING
, 0x25},
73 {EFI_COMPUTING_UNIT_MEMORY
| EFI_CU_MEMORY_PC_OPTIMIZING
, 0x26},
74 {EFI_COMPUTING_UNIT_MEMORY
| EFI_CU_MEMORY_PC_CONFIGURING
, 0x27},
75 {EFI_COMPUTING_UNIT_MEMORY
| EFI_CU_MEMORY_PC_TEST
, 0x28},
76 {EFI_COMPUTING_UNIT_MEMORY
| EFI_CU_MEMORY_PC_COMPLETE
, 0x29},
79 // Platform Init after MRC
81 {EFI_COMPUTING_UNIT_MEMORY
| EFI_CU_MEMORY_PC_PROG_MTRR
, 0x2A},
82 {EFI_COMPUTING_UNIT_MEMORY
| EFI_CU_MEMORY_PC_PROG_MTRR_END
, 0x2B},
84 {EFI_SOFTWARE_PEI_MODULE
| EFI_SW_PEIM_PC_RECOVERY_BEGIN
, 0x31},
85 {EFI_SOFTWARE_PEI_MODULE
| EFI_SW_PEIM_PC_RECOVERY_AUTO
, 0x32},
86 {EFI_SOFTWARE_PEI_MODULE
| EFI_SW_PEIM_PC_CAPSULE_LOAD
, 0x33},
87 {EFI_SOFTWARE_PEI_MODULE
| EFI_SW_PEIM_PC_CAPSULE_START
, 0x34},
88 {EFI_SOFTWARE_PEI_MODULE
| EFI_SW_PEIM_EC_NO_RECOVERY_CAPSULE
, 0x35},
90 {EFI_COMPUTING_UNIT_HOST_PROCESSOR
| EFI_CU_HP_PC_PEI_INIT
, 0x41},
91 {EFI_COMPUTING_UNIT_HOST_PROCESSOR
| EFI_CU_HP_PC_PEI_STEP1
, 0x42},
92 {EFI_COMPUTING_UNIT_HOST_PROCESSOR
| EFI_CU_HP_PC_PEI_END
, 0x43},
93 {EFI_COMPUTING_UNIT_HOST_PROCESSOR
| EFI_CU_HP_PC_SMM_PEI_INIT
, 0x44},
94 {EFI_COMPUTING_UNIT_HOST_PROCESSOR
| EFI_CU_HP_PC_SMM_PEI_STEP1
, 0x45},
95 {EFI_COMPUTING_UNIT_HOST_PROCESSOR
| EFI_CU_HP_PC_SMM_PEI_END
, 0x46}
99 PeiCodeTypeToPostCode (
100 IN EFI_STATUS_CODE_TYPE CodeType
,
101 IN EFI_STATUS_CODE_VALUE Value
,
107 if (CodeType
== EFI_PROGRESS_CODE
) {
108 if ((Value
== (EFI_SOFTWARE_PEI_CORE
| EFI_SW_PC_INIT_BEGIN
)) ||
109 (Value
== (EFI_SOFTWARE_PEI_CORE
| EFI_SW_PC_INIT_END
)) ||
110 (Value
== (EFI_SOFTWARE_DXE_CORE
| EFI_SW_PC_INIT_BEGIN
)) ||
111 (Value
== (EFI_SOFTWARE_DXE_CORE
| EFI_SW_PC_INIT_END
))) {
118 for (Index
= 0; Index
< sizeof(mPeiPort80Table
)/sizeof(EFI_STATUS_CODE_TO_PORT_80
); Index
++) {
119 if (mPeiPort80Table
[Index
].StatusValue
== Value
) {
120 *PostCode
= mPeiPort80Table
[Index
].Port80Value
;