2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include "qemu/osdep.h"
29 #include "qapi/error.h"
30 #include "qemu-common.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/boards.h"
34 #include "hw/loader.h"
36 #include "exec/memory.h"
37 #include "exec/address-spaces.h"
38 #include "hw/char/serial.h"
40 #include "hw/sysbus.h"
41 #include "hw/block/flash.h"
42 #include "sysemu/block-backend.h"
43 #include "chardev/char.h"
44 #include "sysemu/device_tree.h"
45 #include "qemu/error-report.h"
46 #include "bootparam.h"
47 #include "xtensa_memory.h"
49 typedef struct XtfpgaBoardDesc
{
52 size_t flash_boot_base
;
53 size_t flash_sector_size
;
57 typedef struct XtfpgaFpgaState
{
63 static void xtfpga_fpga_reset(void *opaque
)
65 XtfpgaFpgaState
*s
= opaque
;
71 static uint64_t xtfpga_fpga_read(void *opaque
, hwaddr addr
,
74 XtfpgaFpgaState
*s
= opaque
;
77 case 0x0: /*build date code*/
80 case 0x4: /*processor clock frequency, Hz*/
83 case 0x8: /*LEDs (off = 0, on = 1)*/
86 case 0xc: /*DIP switches (off = 0, on = 1)*/
92 static void xtfpga_fpga_write(void *opaque
, hwaddr addr
,
93 uint64_t val
, unsigned size
)
95 XtfpgaFpgaState
*s
= opaque
;
98 case 0x8: /*LEDs (off = 0, on = 1)*/
102 case 0x10: /*board reset*/
104 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
110 static const MemoryRegionOps xtfpga_fpga_ops
= {
111 .read
= xtfpga_fpga_read
,
112 .write
= xtfpga_fpga_write
,
113 .endianness
= DEVICE_NATIVE_ENDIAN
,
116 static XtfpgaFpgaState
*xtfpga_fpga_init(MemoryRegion
*address_space
,
119 XtfpgaFpgaState
*s
= g_malloc(sizeof(XtfpgaFpgaState
));
121 memory_region_init_io(&s
->iomem
, NULL
, &xtfpga_fpga_ops
, s
,
122 "xtfpga.fpga", 0x10000);
123 memory_region_add_subregion(address_space
, base
, &s
->iomem
);
124 xtfpga_fpga_reset(s
);
125 qemu_register_reset(xtfpga_fpga_reset
, s
);
129 static void xtfpga_net_init(MemoryRegion
*address_space
,
133 qemu_irq irq
, NICInfo
*nd
)
139 dev
= qdev_create(NULL
, "open_eth");
140 qdev_set_nic_properties(dev
, nd
);
141 qdev_init_nofail(dev
);
143 s
= SYS_BUS_DEVICE(dev
);
144 sysbus_connect_irq(s
, 0, irq
);
145 memory_region_add_subregion(address_space
, base
,
146 sysbus_mmio_get_region(s
, 0));
147 memory_region_add_subregion(address_space
, descriptors
,
148 sysbus_mmio_get_region(s
, 1));
150 ram
= g_malloc(sizeof(*ram
));
151 memory_region_init_ram_nomigrate(ram
, OBJECT(s
), "open_eth.ram", 16384,
153 vmstate_register_ram_global(ram
);
154 memory_region_add_subregion(address_space
, buffers
, ram
);
157 static pflash_t
*xtfpga_flash_init(MemoryRegion
*address_space
,
158 const XtfpgaBoardDesc
*board
,
159 DriveInfo
*dinfo
, int be
)
162 DeviceState
*dev
= qdev_create(NULL
, "cfi.pflash01");
164 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
166 qdev_prop_set_uint32(dev
, "num-blocks",
167 board
->flash_size
/ board
->flash_sector_size
);
168 qdev_prop_set_uint64(dev
, "sector-length", board
->flash_sector_size
);
169 qdev_prop_set_uint8(dev
, "width", 2);
170 qdev_prop_set_bit(dev
, "big-endian", be
);
171 qdev_prop_set_string(dev
, "name", "xtfpga.io.flash");
172 qdev_init_nofail(dev
);
173 s
= SYS_BUS_DEVICE(dev
);
174 memory_region_add_subregion(address_space
, board
->flash_base
,
175 sysbus_mmio_get_region(s
, 0));
176 return OBJECT_CHECK(pflash_t
, (dev
), "cfi.pflash01");
179 static uint64_t translate_phys_addr(void *opaque
, uint64_t addr
)
181 XtensaCPU
*cpu
= opaque
;
183 return cpu_get_phys_page_debug(CPU(cpu
), addr
);
186 static void xtfpga_reset(void *opaque
)
188 XtensaCPU
*cpu
= opaque
;
193 static uint64_t xtfpga_io_read(void *opaque
, hwaddr addr
,
199 static void xtfpga_io_write(void *opaque
, hwaddr addr
,
200 uint64_t val
, unsigned size
)
204 static const MemoryRegionOps xtfpga_io_ops
= {
205 .read
= xtfpga_io_read
,
206 .write
= xtfpga_io_write
,
207 .endianness
= DEVICE_NATIVE_ENDIAN
,
210 static void xtfpga_init(const XtfpgaBoardDesc
*board
, MachineState
*machine
)
212 #ifdef TARGET_WORDS_BIGENDIAN
217 MemoryRegion
*system_memory
= get_system_memory();
218 XtensaCPU
*cpu
= NULL
;
219 CPUXtensaState
*env
= NULL
;
220 MemoryRegion
*system_io
;
222 pflash_t
*flash
= NULL
;
223 QemuOpts
*machine_opts
= qemu_get_machine_opts();
224 const char *kernel_filename
= qemu_opt_get(machine_opts
, "kernel");
225 const char *kernel_cmdline
= qemu_opt_get(machine_opts
, "append");
226 const char *dtb_filename
= qemu_opt_get(machine_opts
, "dtb");
227 const char *initrd_filename
= qemu_opt_get(machine_opts
, "initrd");
230 for (n
= 0; n
< smp_cpus
; n
++) {
231 cpu
= XTENSA_CPU(cpu_create(machine
->cpu_type
));
234 env
->sregs
[PRID
] = n
;
235 qemu_register_reset(xtfpga_reset
, cpu
);
236 /* Need MMU initialized prior to ELF loading,
237 * so that ELF gets loaded into virtual addresses
243 XtensaMemory sysram
= env
->config
->sysram
;
245 sysram
.location
[0].size
= machine
->ram_size
;
246 xtensa_create_memory_regions(&env
->config
->instrom
, "xtensa.instrom",
248 xtensa_create_memory_regions(&env
->config
->instram
, "xtensa.instram",
250 xtensa_create_memory_regions(&env
->config
->datarom
, "xtensa.datarom",
252 xtensa_create_memory_regions(&env
->config
->dataram
, "xtensa.dataram",
254 xtensa_create_memory_regions(&sysram
, "xtensa.sysram",
258 system_io
= g_malloc(sizeof(*system_io
));
259 memory_region_init_io(system_io
, NULL
, &xtfpga_io_ops
, NULL
, "xtfpga.io",
261 memory_region_add_subregion(system_memory
, 0xf0000000, system_io
);
262 xtfpga_fpga_init(system_io
, 0x0d020000);
263 if (nd_table
[0].used
) {
264 xtfpga_net_init(system_io
, 0x0d030000, 0x0d030400, 0x0d800000,
265 xtensa_get_extint(env
, 1), nd_table
);
268 if (!serial_hds
[0]) {
269 serial_hds
[0] = qemu_chr_new("serial0", "null");
272 serial_mm_init(system_io
, 0x0d050020, 2, xtensa_get_extint(env
, 0),
273 115200, serial_hds
[0], DEVICE_NATIVE_ENDIAN
);
275 dinfo
= drive_get(IF_PFLASH
, 0, 0);
277 flash
= xtfpga_flash_init(system_io
, board
, dinfo
, be
);
280 /* Use presence of kernel file name as 'boot from SRAM' switch. */
281 if (kernel_filename
) {
282 uint32_t entry_point
= env
->pc
;
283 size_t bp_size
= 3 * get_tag_size(0); /* first/last and memory tags */
284 uint32_t tagptr
= env
->config
->sysrom
.location
[0].addr
+
287 BpMemInfo memory_location
= {
288 .type
= tswap32(MEMORY_TYPE_CONVENTIONAL
),
289 .start
= tswap32(env
->config
->sysram
.location
[0].addr
),
290 .end
= tswap32(env
->config
->sysram
.location
[0].addr
+
293 uint32_t lowmem_end
= machine
->ram_size
< 0x08000000 ?
294 machine
->ram_size
: 0x08000000;
295 uint32_t cur_lowmem
= QEMU_ALIGN_UP(lowmem_end
/ 2, 4096);
297 lowmem_end
+= env
->config
->sysram
.location
[0].addr
;
298 cur_lowmem
+= env
->config
->sysram
.location
[0].addr
;
300 xtensa_create_memory_regions(&env
->config
->sysrom
, "xtensa.sysrom",
303 if (kernel_cmdline
) {
304 bp_size
+= get_tag_size(strlen(kernel_cmdline
) + 1);
307 bp_size
+= get_tag_size(sizeof(uint32_t));
309 if (initrd_filename
) {
310 bp_size
+= get_tag_size(sizeof(BpMemInfo
));
313 /* Put kernel bootparameters to the end of that SRAM */
314 tagptr
= (tagptr
- bp_size
) & ~0xff;
315 cur_tagptr
= put_tag(tagptr
, BP_TAG_FIRST
, 0, NULL
);
316 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_MEMORY
,
317 sizeof(memory_location
), &memory_location
);
319 if (kernel_cmdline
) {
320 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_COMMAND_LINE
,
321 strlen(kernel_cmdline
) + 1, kernel_cmdline
);
326 void *fdt
= load_device_tree(dtb_filename
, &fdt_size
);
327 uint32_t dtb_addr
= tswap32(cur_lowmem
);
330 error_report("could not load DTB '%s'", dtb_filename
);
334 cpu_physical_memory_write(cur_lowmem
, fdt
, fdt_size
);
335 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_FDT
,
336 sizeof(dtb_addr
), &dtb_addr
);
337 cur_lowmem
= QEMU_ALIGN_UP(cur_lowmem
+ fdt_size
, 4096);
341 error_report("could not load DTB '%s': "
342 "FDT support is not configured in QEMU",
347 if (initrd_filename
) {
348 BpMemInfo initrd_location
= { 0 };
349 int initrd_size
= load_ramdisk(initrd_filename
, cur_lowmem
,
350 lowmem_end
- cur_lowmem
);
352 if (initrd_size
< 0) {
353 initrd_size
= load_image_targphys(initrd_filename
,
355 lowmem_end
- cur_lowmem
);
357 if (initrd_size
< 0) {
358 error_report("could not load initrd '%s'", initrd_filename
);
361 initrd_location
.start
= tswap32(cur_lowmem
);
362 initrd_location
.end
= tswap32(cur_lowmem
+ initrd_size
);
363 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_INITRD
,
364 sizeof(initrd_location
), &initrd_location
);
365 cur_lowmem
= QEMU_ALIGN_UP(cur_lowmem
+ initrd_size
, 4096);
367 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_LAST
, 0, NULL
);
368 env
->regs
[2] = tagptr
;
371 uint64_t elf_lowaddr
;
372 int success
= load_elf(kernel_filename
, translate_phys_addr
, cpu
,
373 &elf_entry
, &elf_lowaddr
, NULL
, be
, EM_XTENSA
, 0, 0);
375 entry_point
= elf_entry
;
379 success
= load_uimage(kernel_filename
, &ep
, NULL
, &is_linux
,
380 translate_phys_addr
, cpu
);
381 if (success
> 0 && is_linux
) {
384 error_report("could not load kernel '%s'",
389 if (entry_point
!= env
->pc
) {
391 #ifdef TARGET_WORDS_BIGENDIAN
392 0x60, 0x00, 0x08, /* j 1f */
393 0x00, /* .literal_position */
394 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
395 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
397 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */
398 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */
399 0x0a, 0x00, 0x00, /* jx a0 */
401 0x06, 0x02, 0x00, /* j 1f */
402 0x00, /* .literal_position */
403 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
404 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
406 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */
407 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */
408 0xa0, 0x00, 0x00, /* jx a0 */
411 uint32_t entry_pc
= tswap32(entry_point
);
412 uint32_t entry_a2
= tswap32(tagptr
);
414 memcpy(boot
+ 4, &entry_pc
, sizeof(entry_pc
));
415 memcpy(boot
+ 8, &entry_a2
, sizeof(entry_a2
));
416 cpu_physical_memory_write(env
->pc
, boot
, sizeof(boot
));
420 MemoryRegion
*flash_mr
= pflash_cfi01_get_memory(flash
);
421 MemoryRegion
*flash_io
= g_malloc(sizeof(*flash_io
));
422 uint32_t size
= env
->config
->sysrom
.location
[0].size
;
424 if (board
->flash_size
- board
->flash_boot_base
< size
) {
425 size
= board
->flash_size
- board
->flash_boot_base
;
428 memory_region_init_alias(flash_io
, NULL
, "xtfpga.flash",
429 flash_mr
, board
->flash_boot_base
, size
);
430 memory_region_add_subregion(system_memory
,
431 env
->config
->sysrom
.location
[0].addr
,
434 xtensa_create_memory_regions(&env
->config
->sysrom
, "xtensa.sysrom",
440 static void xtfpga_lx60_init(MachineState
*machine
)
442 static const XtfpgaBoardDesc lx60_board
= {
443 .flash_base
= 0x08000000,
444 .flash_size
= 0x00400000,
445 .flash_sector_size
= 0x10000,
446 .sram_size
= 0x20000,
448 xtfpga_init(&lx60_board
, machine
);
451 static void xtfpga_lx200_init(MachineState
*machine
)
453 static const XtfpgaBoardDesc lx200_board
= {
454 .flash_base
= 0x08000000,
455 .flash_size
= 0x01000000,
456 .flash_sector_size
= 0x20000,
457 .sram_size
= 0x2000000,
459 xtfpga_init(&lx200_board
, machine
);
462 static void xtfpga_ml605_init(MachineState
*machine
)
464 static const XtfpgaBoardDesc ml605_board
= {
465 .flash_base
= 0x08000000,
466 .flash_size
= 0x01000000,
467 .flash_sector_size
= 0x20000,
468 .sram_size
= 0x2000000,
470 xtfpga_init(&ml605_board
, machine
);
473 static void xtfpga_kc705_init(MachineState
*machine
)
475 static const XtfpgaBoardDesc kc705_board
= {
476 .flash_base
= 0x00000000,
477 .flash_size
= 0x08000000,
478 .flash_boot_base
= 0x06000000,
479 .flash_sector_size
= 0x20000,
480 .sram_size
= 0x2000000,
482 xtfpga_init(&kc705_board
, machine
);
485 static void xtfpga_lx60_class_init(ObjectClass
*oc
, void *data
)
487 MachineClass
*mc
= MACHINE_CLASS(oc
);
489 mc
->desc
= "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL
")";
490 mc
->init
= xtfpga_lx60_init
;
492 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_TYPE
;
495 static const TypeInfo xtfpga_lx60_type
= {
496 .name
= MACHINE_TYPE_NAME("lx60"),
497 .parent
= TYPE_MACHINE
,
498 .class_init
= xtfpga_lx60_class_init
,
501 static void xtfpga_lx200_class_init(ObjectClass
*oc
, void *data
)
503 MachineClass
*mc
= MACHINE_CLASS(oc
);
505 mc
->desc
= "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL
")";
506 mc
->init
= xtfpga_lx200_init
;
508 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_TYPE
;
511 static const TypeInfo xtfpga_lx200_type
= {
512 .name
= MACHINE_TYPE_NAME("lx200"),
513 .parent
= TYPE_MACHINE
,
514 .class_init
= xtfpga_lx200_class_init
,
517 static void xtfpga_ml605_class_init(ObjectClass
*oc
, void *data
)
519 MachineClass
*mc
= MACHINE_CLASS(oc
);
521 mc
->desc
= "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL
")";
522 mc
->init
= xtfpga_ml605_init
;
524 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_TYPE
;
527 static const TypeInfo xtfpga_ml605_type
= {
528 .name
= MACHINE_TYPE_NAME("ml605"),
529 .parent
= TYPE_MACHINE
,
530 .class_init
= xtfpga_ml605_class_init
,
533 static void xtfpga_kc705_class_init(ObjectClass
*oc
, void *data
)
535 MachineClass
*mc
= MACHINE_CLASS(oc
);
537 mc
->desc
= "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL
")";
538 mc
->init
= xtfpga_kc705_init
;
540 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_TYPE
;
543 static const TypeInfo xtfpga_kc705_type
= {
544 .name
= MACHINE_TYPE_NAME("kc705"),
545 .parent
= TYPE_MACHINE
,
546 .class_init
= xtfpga_kc705_class_init
,
549 static void xtfpga_machines_init(void)
551 type_register_static(&xtfpga_lx60_type
);
552 type_register_static(&xtfpga_lx200_type
);
553 type_register_static(&xtfpga_ml605_type
);
554 type_register_static(&xtfpga_kc705_type
);
557 type_init(xtfpga_machines_init
)