hw/xtensa/xtfpga.c

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qapi/error.h"
  30 #include "qemu-common.h"
  31 #include "cpu.h"
  32 #include "sysemu/sysemu.h"
  33 #include "hw/boards.h"
  34 #include "hw/loader.h"
  35 #include "elf.h"
  36 #include "exec/memory.h"
  37 #include "exec/address-spaces.h"
  38 #include "hw/char/serial.h"
  39 #include "net/net.h"
  40 #include "hw/sysbus.h"
  41 #include "hw/block/flash.h"
  42 #include "sysemu/block-backend.h"
  43 #include "chardev/char.h"
  44 #include "sysemu/device_tree.h"
  45 #include "qemu/error-report.h"
  46 #include "bootparam.h"
  47 #include "xtensa_memory.h"
  48
  49 typedef struct XtfpgaBoardDesc {
  50     hwaddr flash_base;
  51     size_t flash_size;
  52     size_t flash_boot_base;
  53     size_t flash_sector_size;
  54     size_t sram_size;
  55 } XtfpgaBoardDesc;
  56
  57 typedef struct XtfpgaFpgaState {
  58     MemoryRegion iomem;
  59     uint32_t leds;
  60     uint32_t switches;
  61 } XtfpgaFpgaState;
  62
  63 static void xtfpga_fpga_reset(void *opaque)
  64 {
  65     XtfpgaFpgaState *s = opaque;
  66
  67     s->leds = 0;
  68     s->switches = 0;
  69 }
  70
  71 static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr,
  72         unsigned size)
  73 {
  74     XtfpgaFpgaState *s = opaque;
  75
  76     switch (addr) {
  77     case 0x0: /*build date code*/
  78         return 0x09272011;
  79
  80     case 0x4: /*processor clock frequency, Hz*/
  81         return 10000000;
  82
  83     case 0x8: /*LEDs (off = 0, on = 1)*/
  84         return s->leds;
  85
  86     case 0xc: /*DIP switches (off = 0, on = 1)*/
  87         return s->switches;
  88     }
  89     return 0;
  90 }
  91
  92 static void xtfpga_fpga_write(void *opaque, hwaddr addr,
  93         uint64_t val, unsigned size)
  94 {
  95     XtfpgaFpgaState *s = opaque;
  96
  97     switch (addr) {
  98     case 0x8: /*LEDs (off = 0, on = 1)*/
  99         s->leds = val;
 100         break;
 101
 102     case 0x10: /*board reset*/
 103         if (val == 0xdead) {
 104             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 105         }
 106         break;
 107     }
 108 }
 109
 110 static const MemoryRegionOps xtfpga_fpga_ops = {
 111     .read = xtfpga_fpga_read,
 112     .write = xtfpga_fpga_write,
 113     .endianness = DEVICE_NATIVE_ENDIAN,
 114 };
 115
 116 static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space,
 117         hwaddr base)
 118 {
 119     XtfpgaFpgaState *s = g_malloc(sizeof(XtfpgaFpgaState));
 120
 121     memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s,
 122             "xtfpga.fpga", 0x10000);
 123     memory_region_add_subregion(address_space, base, &s->iomem);
 124     xtfpga_fpga_reset(s);
 125     qemu_register_reset(xtfpga_fpga_reset, s);
 126     return s;
 127 }
 128
 129 static void xtfpga_net_init(MemoryRegion *address_space,
 130         hwaddr base,
 131         hwaddr descriptors,
 132         hwaddr buffers,
 133         qemu_irq irq, NICInfo *nd)
 134 {
 135     DeviceState *dev;
 136     SysBusDevice *s;
 137     MemoryRegion *ram;
 138
 139     dev = qdev_create(NULL, "open_eth");
 140     qdev_set_nic_properties(dev, nd);
 141     qdev_init_nofail(dev);
 142
 143     s = SYS_BUS_DEVICE(dev);
 144     sysbus_connect_irq(s, 0, irq);
 145     memory_region_add_subregion(address_space, base,
 146             sysbus_mmio_get_region(s, 0));
 147     memory_region_add_subregion(address_space, descriptors,
 148             sysbus_mmio_get_region(s, 1));
 149
 150     ram = g_malloc(sizeof(*ram));
 151     memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16384,
 152                            &error_fatal);
 153     vmstate_register_ram_global(ram);
 154     memory_region_add_subregion(address_space, buffers, ram);
 155 }
 156
 157 static pflash_t *xtfpga_flash_init(MemoryRegion *address_space,
 158                                    const XtfpgaBoardDesc *board,
 159                                    DriveInfo *dinfo, int be)
 160 {
 161     SysBusDevice *s;
 162     DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
 163
 164     qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
 165                         &error_abort);
 166     qdev_prop_set_uint32(dev, "num-blocks",
 167                          board->flash_size / board->flash_sector_size);
 168     qdev_prop_set_uint64(dev, "sector-length", board->flash_sector_size);
 169     qdev_prop_set_uint8(dev, "width", 2);
 170     qdev_prop_set_bit(dev, "big-endian", be);
 171     qdev_prop_set_string(dev, "name", "xtfpga.io.flash");
 172     qdev_init_nofail(dev);
 173     s = SYS_BUS_DEVICE(dev);
 174     memory_region_add_subregion(address_space, board->flash_base,
 175                                 sysbus_mmio_get_region(s, 0));
 176     return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01");
 177 }
 178
 179 static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
 180 {
 181     XtensaCPU *cpu = opaque;
 182
 183     return cpu_get_phys_page_debug(CPU(cpu), addr);
 184 }
 185
 186 static void xtfpga_reset(void *opaque)
 187 {
 188     XtensaCPU *cpu = opaque;
 189
 190     cpu_reset(CPU(cpu));
 191 }
 192
 193 static uint64_t xtfpga_io_read(void *opaque, hwaddr addr,
 194         unsigned size)
 195 {
 196     return 0;
 197 }
 198
 199 static void xtfpga_io_write(void *opaque, hwaddr addr,
 200         uint64_t val, unsigned size)
 201 {
 202 }
 203
 204 static const MemoryRegionOps xtfpga_io_ops = {
 205     .read = xtfpga_io_read,
 206     .write = xtfpga_io_write,
 207     .endianness = DEVICE_NATIVE_ENDIAN,
 208 };
 209
 210 static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine)
 211 {
 212 #ifdef TARGET_WORDS_BIGENDIAN
 213     int be = 1;
 214 #else
 215     int be = 0;
 216 #endif
 217     MemoryRegion *system_memory = get_system_memory();
 218     XtensaCPU *cpu = NULL;
 219     CPUXtensaState *env = NULL;
 220     MemoryRegion *system_io;
 221     DriveInfo *dinfo;
 222     pflash_t *flash = NULL;
 223     QemuOpts *machine_opts = qemu_get_machine_opts();
 224     const char *kernel_filename = qemu_opt_get(machine_opts, "kernel");
 225     const char *kernel_cmdline = qemu_opt_get(machine_opts, "append");
 226     const char *dtb_filename = qemu_opt_get(machine_opts, "dtb");
 227     const char *initrd_filename = qemu_opt_get(machine_opts, "initrd");
 228     int n;
 229
 230     for (n = 0; n < smp_cpus; n++) {
 231         cpu = XTENSA_CPU(cpu_create(machine->cpu_type));
 232         env = &cpu->env;
 233
 234         env->sregs[PRID] = n;
 235         qemu_register_reset(xtfpga_reset, cpu);
 236         /* Need MMU initialized prior to ELF loading,
 237          * so that ELF gets loaded into virtual addresses
 238          */
 239         cpu_reset(CPU(cpu));
 240     }
 241
 242     if (env) {
 243         XtensaMemory sysram = env->config->sysram;
 244
 245         sysram.location[0].size = machine->ram_size;
 246         xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom",
 247                                      system_memory);
 248         xtensa_create_memory_regions(&env->config->instram, "xtensa.instram",
 249                                      system_memory);
 250         xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom",
 251                                      system_memory);
 252         xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram",
 253                                      system_memory);
 254         xtensa_create_memory_regions(&sysram, "xtensa.sysram",
 255                                      system_memory);
 256     }
 257
 258     system_io = g_malloc(sizeof(*system_io));
 259     memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io",
 260                           224 * 1024 * 1024);
 261     memory_region_add_subregion(system_memory, 0xf0000000, system_io);
 262     xtfpga_fpga_init(system_io, 0x0d020000);
 263     if (nd_table[0].used) {
 264         xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
 265                 xtensa_get_extint(env, 1), nd_table);
 266     }
 267
 268     if (!serial_hds[0]) {
 269         serial_hds[0] = qemu_chr_new("serial0", "null");
 270     }
 271
 272     serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0),
 273             115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
 274
 275     dinfo = drive_get(IF_PFLASH, 0, 0);
 276     if (dinfo) {
 277         flash = xtfpga_flash_init(system_io, board, dinfo, be);
 278     }
 279
 280     /* Use presence of kernel file name as 'boot from SRAM' switch. */
 281     if (kernel_filename) {
 282         uint32_t entry_point = env->pc;
 283         size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */
 284         uint32_t tagptr = env->config->sysrom.location[0].addr +
 285             board->sram_size;
 286         uint32_t cur_tagptr;
 287         BpMemInfo memory_location = {
 288             .type = tswap32(MEMORY_TYPE_CONVENTIONAL),
 289             .start = tswap32(env->config->sysram.location[0].addr),
 290             .end = tswap32(env->config->sysram.location[0].addr +
 291                            machine->ram_size),
 292         };
 293         uint32_t lowmem_end = machine->ram_size < 0x08000000 ?
 294             machine->ram_size : 0x08000000;
 295         uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096);
 296
 297         lowmem_end += env->config->sysram.location[0].addr;
 298         cur_lowmem += env->config->sysram.location[0].addr;
 299
 300         xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
 301                                      system_memory);
 302
 303         if (kernel_cmdline) {
 304             bp_size += get_tag_size(strlen(kernel_cmdline) + 1);
 305         }
 306         if (dtb_filename) {
 307             bp_size += get_tag_size(sizeof(uint32_t));
 308         }
 309         if (initrd_filename) {
 310             bp_size += get_tag_size(sizeof(BpMemInfo));
 311         }
 312
 313         /* Put kernel bootparameters to the end of that SRAM */
 314         tagptr = (tagptr - bp_size) & ~0xff;
 315         cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL);
 316         cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY,
 317                              sizeof(memory_location), &memory_location);
 318
 319         if (kernel_cmdline) {
 320             cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE,
 321                                  strlen(kernel_cmdline) + 1, kernel_cmdline);
 322         }
 323 #ifdef CONFIG_FDT
 324         if (dtb_filename) {
 325             int fdt_size;
 326             void *fdt = load_device_tree(dtb_filename, &fdt_size);
 327             uint32_t dtb_addr = tswap32(cur_lowmem);
 328
 329             if (!fdt) {
 330                 error_report("could not load DTB '%s'", dtb_filename);
 331                 exit(EXIT_FAILURE);
 332             }
 333
 334             cpu_physical_memory_write(cur_lowmem, fdt, fdt_size);
 335             cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT,
 336                                  sizeof(dtb_addr), &dtb_addr);
 337             cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4096);
 338         }
 339 #else
 340         if (dtb_filename) {
 341             error_report("could not load DTB '%s': "
 342                          "FDT support is not configured in QEMU",
 343                          dtb_filename);
 344             exit(EXIT_FAILURE);
 345         }
 346 #endif
 347         if (initrd_filename) {
 348             BpMemInfo initrd_location = { 0 };
 349             int initrd_size = load_ramdisk(initrd_filename, cur_lowmem,
 350                                            lowmem_end - cur_lowmem);
 351
 352             if (initrd_size < 0) {
 353                 initrd_size = load_image_targphys(initrd_filename,
 354                                                   cur_lowmem,
 355                                                   lowmem_end - cur_lowmem);
 356             }
 357             if (initrd_size < 0) {
 358                 error_report("could not load initrd '%s'", initrd_filename);
 359                 exit(EXIT_FAILURE);
 360             }
 361             initrd_location.start = tswap32(cur_lowmem);
 362             initrd_location.end = tswap32(cur_lowmem + initrd_size);
 363             cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD,
 364                                  sizeof(initrd_location), &initrd_location);
 365             cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4096);
 366         }
 367         cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL);
 368         env->regs[2] = tagptr;
 369
 370         uint64_t elf_entry;
 371         uint64_t elf_lowaddr;
 372         int success = load_elf(kernel_filename, translate_phys_addr, cpu,
 373                 &elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0, 0);
 374         if (success > 0) {
 375             entry_point = elf_entry;
 376         } else {
 377             hwaddr ep;
 378             int is_linux;
 379             success = load_uimage(kernel_filename, &ep, NULL, &is_linux,
 380                                   translate_phys_addr, cpu);
 381             if (success > 0 && is_linux) {
 382                 entry_point = ep;
 383             } else {
 384                 error_report("could not load kernel '%s'",
 385                              kernel_filename);
 386                 exit(EXIT_FAILURE);
 387             }
 388         }
 389         if (entry_point != env->pc) {
 390             uint8_t boot[] = {
 391 #ifdef TARGET_WORDS_BIGENDIAN
 392                 0x60, 0x00, 0x08,       /* j    1f */
 393                 0x00,                   /* .literal_position */
 394                 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
 395                 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
 396                                         /* 1: */
 397                 0x10, 0xff, 0xfe,       /* l32r a0, entry_pc */
 398                 0x12, 0xff, 0xfe,       /* l32r a2, entry_a2 */
 399                 0x0a, 0x00, 0x00,       /* jx   a0 */
 400 #else
 401                 0x06, 0x02, 0x00,       /* j    1f */
 402                 0x00,                   /* .literal_position */
 403                 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
 404                 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
 405                                         /* 1: */
 406                 0x01, 0xfe, 0xff,       /* l32r a0, entry_pc */
 407                 0x21, 0xfe, 0xff,       /* l32r a2, entry_a2 */
 408                 0xa0, 0x00, 0x00,       /* jx   a0 */
 409 #endif
 410             };
 411             uint32_t entry_pc = tswap32(entry_point);
 412             uint32_t entry_a2 = tswap32(tagptr);
 413
 414             memcpy(boot + 4, &entry_pc, sizeof(entry_pc));
 415             memcpy(boot + 8, &entry_a2, sizeof(entry_a2));
 416             cpu_physical_memory_write(env->pc, boot, sizeof(boot));
 417         }
 418     } else {
 419         if (flash) {
 420             MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
 421             MemoryRegion *flash_io = g_malloc(sizeof(*flash_io));
 422             uint32_t size = env->config->sysrom.location[0].size;
 423
 424             if (board->flash_size - board->flash_boot_base < size) {
 425                 size = board->flash_size - board->flash_boot_base;
 426             }
 427
 428             memory_region_init_alias(flash_io, NULL, "xtfpga.flash",
 429                                      flash_mr, board->flash_boot_base, size);
 430             memory_region_add_subregion(system_memory,
 431                                         env->config->sysrom.location[0].addr,
 432                                         flash_io);
 433         } else {
 434             xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom",
 435                                          system_memory);
 436         }
 437     }
 438 }
 439
 440 static void xtfpga_lx60_init(MachineState *machine)
 441 {
 442     static const XtfpgaBoardDesc lx60_board = {
 443         .flash_base = 0x08000000,
 444         .flash_size = 0x00400000,
 445         .flash_sector_size = 0x10000,
 446         .sram_size = 0x20000,
 447     };
 448     xtfpga_init(&lx60_board, machine);
 449 }
 450
 451 static void xtfpga_lx200_init(MachineState *machine)
 452 {
 453     static const XtfpgaBoardDesc lx200_board = {
 454         .flash_base = 0x08000000,
 455         .flash_size = 0x01000000,
 456         .flash_sector_size = 0x20000,
 457         .sram_size = 0x2000000,
 458     };
 459     xtfpga_init(&lx200_board, machine);
 460 }
 461
 462 static void xtfpga_ml605_init(MachineState *machine)
 463 {
 464     static const XtfpgaBoardDesc ml605_board = {
 465         .flash_base = 0x08000000,
 466         .flash_size = 0x01000000,
 467         .flash_sector_size = 0x20000,
 468         .sram_size = 0x2000000,
 469     };
 470     xtfpga_init(&ml605_board, machine);
 471 }
 472
 473 static void xtfpga_kc705_init(MachineState *machine)
 474 {
 475     static const XtfpgaBoardDesc kc705_board = {
 476         .flash_base = 0x00000000,
 477         .flash_size = 0x08000000,
 478         .flash_boot_base = 0x06000000,
 479         .flash_sector_size = 0x20000,
 480         .sram_size = 0x2000000,
 481     };
 482     xtfpga_init(&kc705_board, machine);
 483 }
 484
 485 static void xtfpga_lx60_class_init(ObjectClass *oc, void *data)
 486 {
 487     MachineClass *mc = MACHINE_CLASS(oc);
 488
 489     mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 490     mc->init = xtfpga_lx60_init;
 491     mc->max_cpus = 4;
 492     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
 493 }
 494
 495 static const TypeInfo xtfpga_lx60_type = {
 496     .name = MACHINE_TYPE_NAME("lx60"),
 497     .parent = TYPE_MACHINE,
 498     .class_init = xtfpga_lx60_class_init,
 499 };
 500
 501 static void xtfpga_lx200_class_init(ObjectClass *oc, void *data)
 502 {
 503     MachineClass *mc = MACHINE_CLASS(oc);
 504
 505     mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 506     mc->init = xtfpga_lx200_init;
 507     mc->max_cpus = 4;
 508     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
 509 }
 510
 511 static const TypeInfo xtfpga_lx200_type = {
 512     .name = MACHINE_TYPE_NAME("lx200"),
 513     .parent = TYPE_MACHINE,
 514     .class_init = xtfpga_lx200_class_init,
 515 };
 516
 517 static void xtfpga_ml605_class_init(ObjectClass *oc, void *data)
 518 {
 519     MachineClass *mc = MACHINE_CLASS(oc);
 520
 521     mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 522     mc->init = xtfpga_ml605_init;
 523     mc->max_cpus = 4;
 524     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
 525 }
 526
 527 static const TypeInfo xtfpga_ml605_type = {
 528     .name = MACHINE_TYPE_NAME("ml605"),
 529     .parent = TYPE_MACHINE,
 530     .class_init = xtfpga_ml605_class_init,
 531 };
 532
 533 static void xtfpga_kc705_class_init(ObjectClass *oc, void *data)
 534 {
 535     MachineClass *mc = MACHINE_CLASS(oc);
 536
 537     mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
 538     mc->init = xtfpga_kc705_init;
 539     mc->max_cpus = 4;
 540     mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE;
 541 }
 542
 543 static const TypeInfo xtfpga_kc705_type = {
 544     .name = MACHINE_TYPE_NAME("kc705"),
 545     .parent = TYPE_MACHINE,
 546     .class_init = xtfpga_kc705_class_init,
 547 };
 548
 549 static void xtfpga_machines_init(void)
 550 {
 551     type_register_static(&xtfpga_lx60_type);
 552     type_register_static(&xtfpga_lx200_type);
 553     type_register_static(&xtfpga_ml605_type);
 554     type_register_static(&xtfpga_kc705_type);
 555 }
 556
 557 type_init(xtfpga_machines_init)