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0200db65 MF |
1 | /* |
2 | * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. | |
3 | * All rights reserved. | |
4 | * | |
5 | * Redistribution and use in source and binary forms, with or without | |
6 | * modification, are permitted provided that the following conditions are met: | |
7 | * * Redistributions of source code must retain the above copyright | |
8 | * notice, this list of conditions and the following disclaimer. | |
9 | * * Redistributions in binary form must reproduce the above copyright | |
10 | * notice, this list of conditions and the following disclaimer in the | |
11 | * documentation and/or other materials provided with the distribution. | |
12 | * * Neither the name of the Open Source and Linux Lab nor the | |
13 | * names of its contributors may be used to endorse or promote products | |
14 | * derived from this software without specific prior written permission. | |
15 | * | |
16 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
17 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY | |
20 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
21 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
22 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
23 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
24 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
25 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
26 | */ | |
27 | ||
09aae23d | 28 | #include "qemu/osdep.h" |
da34e65c | 29 | #include "qapi/error.h" |
4771d756 PB |
30 | #include "qemu-common.h" |
31 | #include "cpu.h" | |
9c17d615 | 32 | #include "sysemu/sysemu.h" |
83c9f4ca PB |
33 | #include "hw/boards.h" |
34 | #include "hw/loader.h" | |
0200db65 | 35 | #include "elf.h" |
022c62cb PB |
36 | #include "exec/memory.h" |
37 | #include "exec/address-spaces.h" | |
0d09e41a | 38 | #include "hw/char/serial.h" |
1422e32d | 39 | #include "net/net.h" |
83c9f4ca | 40 | #include "hw/sysbus.h" |
0d09e41a | 41 | #include "hw/block/flash.h" |
fa1d36df | 42 | #include "sysemu/block-backend.h" |
8228e353 | 43 | #include "chardev/char.h" |
996dfe98 | 44 | #include "sysemu/device_tree.h" |
8488ab02 | 45 | #include "qemu/error-report.h" |
b707ab75 | 46 | #include "bootparam.h" |
e53fa62c | 47 | #include "xtensa_memory.h" |
82b25dc8 | 48 | |
188ce01d | 49 | typedef struct XtfpgaBoardDesc { |
e0db904d | 50 | hwaddr flash_base; |
82b25dc8 | 51 | size_t flash_size; |
37ed7c4b | 52 | size_t flash_boot_base; |
82b25dc8 MF |
53 | size_t flash_sector_size; |
54 | size_t sram_size; | |
188ce01d | 55 | } XtfpgaBoardDesc; |
0200db65 | 56 | |
188ce01d | 57 | typedef struct XtfpgaFpgaState { |
0200db65 MF |
58 | MemoryRegion iomem; |
59 | uint32_t leds; | |
60 | uint32_t switches; | |
188ce01d | 61 | } XtfpgaFpgaState; |
0200db65 | 62 | |
188ce01d | 63 | static void xtfpga_fpga_reset(void *opaque) |
0200db65 | 64 | { |
188ce01d | 65 | XtfpgaFpgaState *s = opaque; |
0200db65 MF |
66 | |
67 | s->leds = 0; | |
68 | s->switches = 0; | |
69 | } | |
70 | ||
188ce01d | 71 | static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr, |
0200db65 MF |
72 | unsigned size) |
73 | { | |
188ce01d | 74 | XtfpgaFpgaState *s = opaque; |
0200db65 MF |
75 | |
76 | switch (addr) { | |
77 | case 0x0: /*build date code*/ | |
556ba668 | 78 | return 0x09272011; |
0200db65 MF |
79 | |
80 | case 0x4: /*processor clock frequency, Hz*/ | |
81 | return 10000000; | |
82 | ||
83 | case 0x8: /*LEDs (off = 0, on = 1)*/ | |
84 | return s->leds; | |
85 | ||
86 | case 0xc: /*DIP switches (off = 0, on = 1)*/ | |
87 | return s->switches; | |
88 | } | |
89 | return 0; | |
90 | } | |
91 | ||
188ce01d | 92 | static void xtfpga_fpga_write(void *opaque, hwaddr addr, |
0200db65 MF |
93 | uint64_t val, unsigned size) |
94 | { | |
188ce01d | 95 | XtfpgaFpgaState *s = opaque; |
0200db65 MF |
96 | |
97 | switch (addr) { | |
98 | case 0x8: /*LEDs (off = 0, on = 1)*/ | |
99 | s->leds = val; | |
100 | break; | |
101 | ||
102 | case 0x10: /*board reset*/ | |
103 | if (val == 0xdead) { | |
cf83f140 | 104 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
0200db65 MF |
105 | } |
106 | break; | |
107 | } | |
108 | } | |
109 | ||
188ce01d MF |
110 | static const MemoryRegionOps xtfpga_fpga_ops = { |
111 | .read = xtfpga_fpga_read, | |
112 | .write = xtfpga_fpga_write, | |
0200db65 MF |
113 | .endianness = DEVICE_NATIVE_ENDIAN, |
114 | }; | |
115 | ||
188ce01d | 116 | static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space, |
a8170e5e | 117 | hwaddr base) |
0200db65 | 118 | { |
188ce01d | 119 | XtfpgaFpgaState *s = g_malloc(sizeof(XtfpgaFpgaState)); |
0200db65 | 120 | |
188ce01d MF |
121 | memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s, |
122 | "xtfpga.fpga", 0x10000); | |
0200db65 | 123 | memory_region_add_subregion(address_space, base, &s->iomem); |
188ce01d MF |
124 | xtfpga_fpga_reset(s); |
125 | qemu_register_reset(xtfpga_fpga_reset, s); | |
0200db65 MF |
126 | return s; |
127 | } | |
128 | ||
188ce01d | 129 | static void xtfpga_net_init(MemoryRegion *address_space, |
a8170e5e AK |
130 | hwaddr base, |
131 | hwaddr descriptors, | |
132 | hwaddr buffers, | |
0200db65 MF |
133 | qemu_irq irq, NICInfo *nd) |
134 | { | |
135 | DeviceState *dev; | |
136 | SysBusDevice *s; | |
137 | MemoryRegion *ram; | |
138 | ||
139 | dev = qdev_create(NULL, "open_eth"); | |
140 | qdev_set_nic_properties(dev, nd); | |
141 | qdev_init_nofail(dev); | |
142 | ||
1356b98d | 143 | s = SYS_BUS_DEVICE(dev); |
0200db65 MF |
144 | sysbus_connect_irq(s, 0, irq); |
145 | memory_region_add_subregion(address_space, base, | |
146 | sysbus_mmio_get_region(s, 0)); | |
147 | memory_region_add_subregion(address_space, descriptors, | |
148 | sysbus_mmio_get_region(s, 1)); | |
149 | ||
150 | ram = g_malloc(sizeof(*ram)); | |
1cfe48c1 | 151 | memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16384, |
f8ed85ac | 152 | &error_fatal); |
c5705a77 | 153 | vmstate_register_ram_global(ram); |
0200db65 MF |
154 | memory_region_add_subregion(address_space, buffers, ram); |
155 | } | |
156 | ||
68931a40 | 157 | static pflash_t *xtfpga_flash_init(MemoryRegion *address_space, |
188ce01d | 158 | const XtfpgaBoardDesc *board, |
68931a40 MF |
159 | DriveInfo *dinfo, int be) |
160 | { | |
161 | SysBusDevice *s; | |
162 | DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); | |
163 | ||
164 | qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), | |
165 | &error_abort); | |
166 | qdev_prop_set_uint32(dev, "num-blocks", | |
167 | board->flash_size / board->flash_sector_size); | |
168 | qdev_prop_set_uint64(dev, "sector-length", board->flash_sector_size); | |
f9a555e4 | 169 | qdev_prop_set_uint8(dev, "width", 2); |
68931a40 | 170 | qdev_prop_set_bit(dev, "big-endian", be); |
188ce01d | 171 | qdev_prop_set_string(dev, "name", "xtfpga.io.flash"); |
68931a40 MF |
172 | qdev_init_nofail(dev); |
173 | s = SYS_BUS_DEVICE(dev); | |
174 | memory_region_add_subregion(address_space, board->flash_base, | |
175 | sysbus_mmio_get_region(s, 0)); | |
176 | return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01"); | |
177 | } | |
178 | ||
00b941e5 | 179 | static uint64_t translate_phys_addr(void *opaque, uint64_t addr) |
0200db65 | 180 | { |
00b941e5 AF |
181 | XtensaCPU *cpu = opaque; |
182 | ||
183 | return cpu_get_phys_page_debug(CPU(cpu), addr); | |
0200db65 MF |
184 | } |
185 | ||
188ce01d | 186 | static void xtfpga_reset(void *opaque) |
0200db65 | 187 | { |
eded1267 | 188 | XtensaCPU *cpu = opaque; |
1bba0dc9 | 189 | |
eded1267 | 190 | cpu_reset(CPU(cpu)); |
0200db65 MF |
191 | } |
192 | ||
188ce01d | 193 | static uint64_t xtfpga_io_read(void *opaque, hwaddr addr, |
8bb3b575 MF |
194 | unsigned size) |
195 | { | |
196 | return 0; | |
197 | } | |
198 | ||
188ce01d | 199 | static void xtfpga_io_write(void *opaque, hwaddr addr, |
8bb3b575 MF |
200 | uint64_t val, unsigned size) |
201 | { | |
202 | } | |
203 | ||
188ce01d MF |
204 | static const MemoryRegionOps xtfpga_io_ops = { |
205 | .read = xtfpga_io_read, | |
206 | .write = xtfpga_io_write, | |
8bb3b575 MF |
207 | .endianness = DEVICE_NATIVE_ENDIAN, |
208 | }; | |
209 | ||
188ce01d | 210 | static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) |
0200db65 MF |
211 | { |
212 | #ifdef TARGET_WORDS_BIGENDIAN | |
213 | int be = 1; | |
214 | #else | |
215 | int be = 0; | |
216 | #endif | |
217 | MemoryRegion *system_memory = get_system_memory(); | |
adbb0f75 | 218 | XtensaCPU *cpu = NULL; |
5bfcb36e | 219 | CPUXtensaState *env = NULL; |
e53fa62c | 220 | MemoryRegion *system_io; |
82b25dc8 MF |
221 | DriveInfo *dinfo; |
222 | pflash_t *flash = NULL; | |
37b259d0 | 223 | QemuOpts *machine_opts = qemu_get_machine_opts(); |
37b259d0 MF |
224 | const char *kernel_filename = qemu_opt_get(machine_opts, "kernel"); |
225 | const char *kernel_cmdline = qemu_opt_get(machine_opts, "append"); | |
996dfe98 | 226 | const char *dtb_filename = qemu_opt_get(machine_opts, "dtb"); |
f55b32e7 | 227 | const char *initrd_filename = qemu_opt_get(machine_opts, "initrd"); |
0200db65 MF |
228 | int n; |
229 | ||
230 | for (n = 0; n < smp_cpus; n++) { | |
f83eb10d | 231 | cpu = XTENSA_CPU(cpu_create(machine->cpu_type)); |
adbb0f75 AF |
232 | env = &cpu->env; |
233 | ||
0200db65 | 234 | env->sregs[PRID] = n; |
188ce01d | 235 | qemu_register_reset(xtfpga_reset, cpu); |
0200db65 MF |
236 | /* Need MMU initialized prior to ELF loading, |
237 | * so that ELF gets loaded into virtual addresses | |
238 | */ | |
adbb0f75 | 239 | cpu_reset(CPU(cpu)); |
0200db65 MF |
240 | } |
241 | ||
e53fa62c MF |
242 | if (env) { |
243 | XtensaMemory sysram = env->config->sysram; | |
244 | ||
245 | sysram.location[0].size = machine->ram_size; | |
246 | xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom", | |
247 | system_memory); | |
248 | xtensa_create_memory_regions(&env->config->instram, "xtensa.instram", | |
249 | system_memory); | |
250 | xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom", | |
251 | system_memory); | |
252 | xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram", | |
253 | system_memory); | |
254 | xtensa_create_memory_regions(&sysram, "xtensa.sysram", | |
255 | system_memory); | |
256 | } | |
0200db65 | 257 | |
0200db65 | 258 | system_io = g_malloc(sizeof(*system_io)); |
188ce01d | 259 | memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io", |
8bb3b575 | 260 | 224 * 1024 * 1024); |
0200db65 | 261 | memory_region_add_subregion(system_memory, 0xf0000000, system_io); |
188ce01d | 262 | xtfpga_fpga_init(system_io, 0x0d020000); |
a005d073 | 263 | if (nd_table[0].used) { |
188ce01d | 264 | xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, |
0200db65 MF |
265 | xtensa_get_extint(env, 1), nd_table); |
266 | } | |
267 | ||
268 | if (!serial_hds[0]) { | |
b4948be9 | 269 | serial_hds[0] = qemu_chr_new("serial0", "null"); |
0200db65 MF |
270 | } |
271 | ||
272 | serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0), | |
273 | 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); | |
274 | ||
82b25dc8 MF |
275 | dinfo = drive_get(IF_PFLASH, 0, 0); |
276 | if (dinfo) { | |
68931a40 | 277 | flash = xtfpga_flash_init(system_io, board, dinfo, be); |
82b25dc8 MF |
278 | } |
279 | ||
280 | /* Use presence of kernel file name as 'boot from SRAM' switch. */ | |
0200db65 | 281 | if (kernel_filename) { |
364d4802 | 282 | uint32_t entry_point = env->pc; |
b6edea8b | 283 | size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */ |
e53fa62c MF |
284 | uint32_t tagptr = env->config->sysrom.location[0].addr + |
285 | board->sram_size; | |
a9a28591 | 286 | uint32_t cur_tagptr; |
b6edea8b MF |
287 | BpMemInfo memory_location = { |
288 | .type = tswap32(MEMORY_TYPE_CONVENTIONAL), | |
e53fa62c MF |
289 | .start = tswap32(env->config->sysram.location[0].addr), |
290 | .end = tswap32(env->config->sysram.location[0].addr + | |
291 | machine->ram_size), | |
b6edea8b | 292 | }; |
996dfe98 MF |
293 | uint32_t lowmem_end = machine->ram_size < 0x08000000 ? |
294 | machine->ram_size : 0x08000000; | |
295 | uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096); | |
a9a28591 | 296 | |
e53fa62c MF |
297 | lowmem_end += env->config->sysram.location[0].addr; |
298 | cur_lowmem += env->config->sysram.location[0].addr; | |
299 | ||
300 | xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", | |
301 | system_memory); | |
292627bb | 302 | |
a9a28591 MF |
303 | if (kernel_cmdline) { |
304 | bp_size += get_tag_size(strlen(kernel_cmdline) + 1); | |
305 | } | |
996dfe98 MF |
306 | if (dtb_filename) { |
307 | bp_size += get_tag_size(sizeof(uint32_t)); | |
308 | } | |
f55b32e7 MF |
309 | if (initrd_filename) { |
310 | bp_size += get_tag_size(sizeof(BpMemInfo)); | |
311 | } | |
a9a28591 | 312 | |
292627bb | 313 | /* Put kernel bootparameters to the end of that SRAM */ |
a9a28591 MF |
314 | tagptr = (tagptr - bp_size) & ~0xff; |
315 | cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL); | |
b6edea8b MF |
316 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY, |
317 | sizeof(memory_location), &memory_location); | |
a9a28591 | 318 | |
292627bb | 319 | if (kernel_cmdline) { |
a9a28591 MF |
320 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE, |
321 | strlen(kernel_cmdline) + 1, kernel_cmdline); | |
292627bb | 322 | } |
0e80359e | 323 | #ifdef CONFIG_FDT |
996dfe98 MF |
324 | if (dtb_filename) { |
325 | int fdt_size; | |
326 | void *fdt = load_device_tree(dtb_filename, &fdt_size); | |
327 | uint32_t dtb_addr = tswap32(cur_lowmem); | |
328 | ||
329 | if (!fdt) { | |
ebbb419a | 330 | error_report("could not load DTB '%s'", dtb_filename); |
996dfe98 MF |
331 | exit(EXIT_FAILURE); |
332 | } | |
333 | ||
334 | cpu_physical_memory_write(cur_lowmem, fdt, fdt_size); | |
335 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT, | |
336 | sizeof(dtb_addr), &dtb_addr); | |
337 | cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4096); | |
338 | } | |
0e80359e MF |
339 | #else |
340 | if (dtb_filename) { | |
341 | error_report("could not load DTB '%s': " | |
342 | "FDT support is not configured in QEMU", | |
343 | dtb_filename); | |
344 | exit(EXIT_FAILURE); | |
345 | } | |
346 | #endif | |
f55b32e7 MF |
347 | if (initrd_filename) { |
348 | BpMemInfo initrd_location = { 0 }; | |
349 | int initrd_size = load_ramdisk(initrd_filename, cur_lowmem, | |
350 | lowmem_end - cur_lowmem); | |
351 | ||
352 | if (initrd_size < 0) { | |
353 | initrd_size = load_image_targphys(initrd_filename, | |
354 | cur_lowmem, | |
355 | lowmem_end - cur_lowmem); | |
356 | } | |
357 | if (initrd_size < 0) { | |
ebbb419a | 358 | error_report("could not load initrd '%s'", initrd_filename); |
f55b32e7 MF |
359 | exit(EXIT_FAILURE); |
360 | } | |
361 | initrd_location.start = tswap32(cur_lowmem); | |
362 | initrd_location.end = tswap32(cur_lowmem + initrd_size); | |
363 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD, | |
364 | sizeof(initrd_location), &initrd_location); | |
365 | cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4096); | |
366 | } | |
a9a28591 MF |
367 | cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL); |
368 | env->regs[2] = tagptr; | |
369 | ||
0200db65 MF |
370 | uint64_t elf_entry; |
371 | uint64_t elf_lowaddr; | |
00b941e5 | 372 | int success = load_elf(kernel_filename, translate_phys_addr, cpu, |
7ef295ea | 373 | &elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0, 0); |
0200db65 | 374 | if (success > 0) { |
364d4802 MF |
375 | entry_point = elf_entry; |
376 | } else { | |
377 | hwaddr ep; | |
378 | int is_linux; | |
25bda50a | 379 | success = load_uimage(kernel_filename, &ep, NULL, &is_linux, |
6d2e4530 | 380 | translate_phys_addr, cpu); |
364d4802 MF |
381 | if (success > 0 && is_linux) { |
382 | entry_point = ep; | |
383 | } else { | |
ebbb419a | 384 | error_report("could not load kernel '%s'", |
364d4802 MF |
385 | kernel_filename); |
386 | exit(EXIT_FAILURE); | |
387 | } | |
388 | } | |
389 | if (entry_point != env->pc) { | |
339ef8fb | 390 | uint8_t boot[] = { |
364d4802 | 391 | #ifdef TARGET_WORDS_BIGENDIAN |
339ef8fb MF |
392 | 0x60, 0x00, 0x08, /* j 1f */ |
393 | 0x00, /* .literal_position */ | |
394 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ | |
395 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ | |
396 | /* 1: */ | |
397 | 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */ | |
398 | 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */ | |
399 | 0x0a, 0x00, 0x00, /* jx a0 */ | |
364d4802 | 400 | #else |
339ef8fb MF |
401 | 0x06, 0x02, 0x00, /* j 1f */ |
402 | 0x00, /* .literal_position */ | |
403 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ | |
404 | 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ | |
405 | /* 1: */ | |
406 | 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */ | |
407 | 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */ | |
408 | 0xa0, 0x00, 0x00, /* jx a0 */ | |
364d4802 MF |
409 | #endif |
410 | }; | |
339ef8fb MF |
411 | uint32_t entry_pc = tswap32(entry_point); |
412 | uint32_t entry_a2 = tswap32(tagptr); | |
413 | ||
414 | memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); | |
415 | memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); | |
416 | cpu_physical_memory_write(env->pc, boot, sizeof(boot)); | |
0200db65 | 417 | } |
82b25dc8 MF |
418 | } else { |
419 | if (flash) { | |
420 | MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); | |
421 | MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); | |
e53fa62c MF |
422 | uint32_t size = env->config->sysrom.location[0].size; |
423 | ||
424 | if (board->flash_size - board->flash_boot_base < size) { | |
425 | size = board->flash_size - board->flash_boot_base; | |
426 | } | |
82b25dc8 | 427 | |
188ce01d | 428 | memory_region_init_alias(flash_io, NULL, "xtfpga.flash", |
e53fa62c MF |
429 | flash_mr, board->flash_boot_base, size); |
430 | memory_region_add_subregion(system_memory, | |
431 | env->config->sysrom.location[0].addr, | |
432 | flash_io); | |
433 | } else { | |
434 | xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", | |
435 | system_memory); | |
82b25dc8 | 436 | } |
0200db65 MF |
437 | } |
438 | } | |
439 | ||
188ce01d | 440 | static void xtfpga_lx60_init(MachineState *machine) |
0200db65 | 441 | { |
188ce01d | 442 | static const XtfpgaBoardDesc lx60_board = { |
68931a40 | 443 | .flash_base = 0x08000000, |
e0db904d | 444 | .flash_size = 0x00400000, |
82b25dc8 MF |
445 | .flash_sector_size = 0x10000, |
446 | .sram_size = 0x20000, | |
447 | }; | |
188ce01d | 448 | xtfpga_init(&lx60_board, machine); |
82b25dc8 MF |
449 | } |
450 | ||
188ce01d | 451 | static void xtfpga_lx200_init(MachineState *machine) |
82b25dc8 | 452 | { |
188ce01d | 453 | static const XtfpgaBoardDesc lx200_board = { |
68931a40 | 454 | .flash_base = 0x08000000, |
e0db904d | 455 | .flash_size = 0x01000000, |
82b25dc8 MF |
456 | .flash_sector_size = 0x20000, |
457 | .sram_size = 0x2000000, | |
458 | }; | |
188ce01d | 459 | xtfpga_init(&lx200_board, machine); |
0200db65 MF |
460 | } |
461 | ||
188ce01d | 462 | static void xtfpga_ml605_init(MachineState *machine) |
e0db904d | 463 | { |
188ce01d | 464 | static const XtfpgaBoardDesc ml605_board = { |
68931a40 | 465 | .flash_base = 0x08000000, |
12004c9e | 466 | .flash_size = 0x01000000, |
e0db904d MF |
467 | .flash_sector_size = 0x20000, |
468 | .sram_size = 0x2000000, | |
469 | }; | |
188ce01d | 470 | xtfpga_init(&ml605_board, machine); |
e0db904d MF |
471 | } |
472 | ||
188ce01d | 473 | static void xtfpga_kc705_init(MachineState *machine) |
e0db904d | 474 | { |
188ce01d | 475 | static const XtfpgaBoardDesc kc705_board = { |
68931a40 | 476 | .flash_base = 0x00000000, |
e0db904d | 477 | .flash_size = 0x08000000, |
37ed7c4b | 478 | .flash_boot_base = 0x06000000, |
e0db904d MF |
479 | .flash_sector_size = 0x20000, |
480 | .sram_size = 0x2000000, | |
481 | }; | |
188ce01d | 482 | xtfpga_init(&kc705_board, machine); |
e0db904d MF |
483 | } |
484 | ||
188ce01d | 485 | static void xtfpga_lx60_class_init(ObjectClass *oc, void *data) |
e264d29d | 486 | { |
8a661aea AF |
487 | MachineClass *mc = MACHINE_CLASS(oc); |
488 | ||
e264d29d | 489 | mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 490 | mc->init = xtfpga_lx60_init; |
e264d29d | 491 | mc->max_cpus = 4; |
f83eb10d | 492 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
e264d29d | 493 | } |
0200db65 | 494 | |
188ce01d | 495 | static const TypeInfo xtfpga_lx60_type = { |
8a661aea AF |
496 | .name = MACHINE_TYPE_NAME("lx60"), |
497 | .parent = TYPE_MACHINE, | |
188ce01d | 498 | .class_init = xtfpga_lx60_class_init, |
8a661aea | 499 | }; |
82b25dc8 | 500 | |
188ce01d | 501 | static void xtfpga_lx200_class_init(ObjectClass *oc, void *data) |
e264d29d | 502 | { |
8a661aea AF |
503 | MachineClass *mc = MACHINE_CLASS(oc); |
504 | ||
e264d29d | 505 | mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 506 | mc->init = xtfpga_lx200_init; |
e264d29d | 507 | mc->max_cpus = 4; |
f83eb10d | 508 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
e264d29d | 509 | } |
e0db904d | 510 | |
188ce01d | 511 | static const TypeInfo xtfpga_lx200_type = { |
8a661aea AF |
512 | .name = MACHINE_TYPE_NAME("lx200"), |
513 | .parent = TYPE_MACHINE, | |
188ce01d | 514 | .class_init = xtfpga_lx200_class_init, |
8a661aea | 515 | }; |
e264d29d | 516 | |
188ce01d | 517 | static void xtfpga_ml605_class_init(ObjectClass *oc, void *data) |
e264d29d | 518 | { |
8a661aea AF |
519 | MachineClass *mc = MACHINE_CLASS(oc); |
520 | ||
e264d29d | 521 | mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 522 | mc->init = xtfpga_ml605_init; |
e264d29d | 523 | mc->max_cpus = 4; |
f83eb10d | 524 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
e264d29d EH |
525 | } |
526 | ||
188ce01d | 527 | static const TypeInfo xtfpga_ml605_type = { |
8a661aea AF |
528 | .name = MACHINE_TYPE_NAME("ml605"), |
529 | .parent = TYPE_MACHINE, | |
188ce01d | 530 | .class_init = xtfpga_ml605_class_init, |
8a661aea | 531 | }; |
e0db904d | 532 | |
188ce01d | 533 | static void xtfpga_kc705_class_init(ObjectClass *oc, void *data) |
0200db65 | 534 | { |
8a661aea AF |
535 | MachineClass *mc = MACHINE_CLASS(oc); |
536 | ||
e264d29d | 537 | mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; |
188ce01d | 538 | mc->init = xtfpga_kc705_init; |
e264d29d | 539 | mc->max_cpus = 4; |
f83eb10d | 540 | mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; |
0200db65 MF |
541 | } |
542 | ||
188ce01d | 543 | static const TypeInfo xtfpga_kc705_type = { |
8a661aea AF |
544 | .name = MACHINE_TYPE_NAME("kc705"), |
545 | .parent = TYPE_MACHINE, | |
188ce01d | 546 | .class_init = xtfpga_kc705_class_init, |
8a661aea AF |
547 | }; |
548 | ||
188ce01d | 549 | static void xtfpga_machines_init(void) |
8a661aea | 550 | { |
188ce01d MF |
551 | type_register_static(&xtfpga_lx60_type); |
552 | type_register_static(&xtfpga_lx200_type); | |
553 | type_register_static(&xtfpga_ml605_type); | |
554 | type_register_static(&xtfpga_kc705_type); | |
8a661aea AF |
555 | } |
556 | ||
188ce01d | 557 | type_init(xtfpga_machines_init) |