module/zfs/vdev_raidz_math_avx2.c

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright (C) 2016 Gvozden Nešković. All rights reserved.
  23  */
  24
  25 #include <sys/isa_defs.h>
  26
  27 #if defined(__x86_64) && defined(HAVE_AVX2)
  28
  29 #include <sys/types.h>
  30 #include <linux/simd_x86.h>
  31
  32 #define __asm __asm__ __volatile__
  33
  34 #define _REG_CNT(_0, _1, _2, _3, _4, _5, _6, _7, N, ...) N
  35 #define REG_CNT(r...) _REG_CNT(r, 8, 7, 6, 5, 4, 3, 2, 1)
  36
  37 #define VR0_(REG, ...) "ymm"#REG
  38 #define VR1_(_1, REG, ...) "ymm"#REG
  39 #define VR2_(_1, _2, REG, ...) "ymm"#REG
  40 #define VR3_(_1, _2, _3, REG, ...) "ymm"#REG
  41 #define VR4_(_1, _2, _3, _4, REG, ...) "ymm"#REG
  42 #define VR5_(_1, _2, _3, _4, _5, REG, ...) "ymm"#REG
  43 #define VR6_(_1, _2, _3, _4, _5, _6, REG, ...) "ymm"#REG
  44 #define VR7_(_1, _2, _3, _4, _5, _6, _7, REG, ...) "ymm"#REG
  45
  46 #define VR0(r...) VR0_(r)
  47 #define VR1(r...) VR1_(r)
  48 #define VR2(r...) VR2_(r, 1)
  49 #define VR3(r...) VR3_(r, 1, 2)
  50 #define VR4(r...) VR4_(r, 1, 2)
  51 #define VR5(r...) VR5_(r, 1, 2, 3)
  52 #define VR6(r...) VR6_(r, 1, 2, 3, 4)
  53 #define VR7(r...) VR7_(r, 1, 2, 3, 4, 5)
  54
  55 #define R_01(REG1, REG2, ...) REG1, REG2
  56 #define _R_23(_0, _1, REG2, REG3, ...) REG2, REG3
  57 #define R_23(REG...) _R_23(REG, 1, 2, 3)
  58
  59 #define ASM_BUG()       ASSERT(0)
  60
  61 extern const uint8_t gf_clmul_mod_lt[4*256][16];
  62
  63 #define ELEM_SIZE 32
  64
  65 typedef struct v {
  66         uint8_t b[ELEM_SIZE] __attribute__((aligned(ELEM_SIZE)));
  67 } v_t;
  68
  69 #define PREFETCHNTA(ptr, offset)                                        \
  70 {                                                                       \
  71         __asm(                                                          \
  72             "prefetchnta " #offset "(%[MEM])\n"                         \
  73             : : [MEM] "r" (ptr));                                       \
  74 }
  75
  76 #define PREFETCH(ptr, offset)                                           \
  77 {                                                                       \
  78         __asm(                                                          \
  79             "prefetcht0 " #offset "(%[MEM])\n"                          \
  80             : : [MEM] "r" (ptr));                                       \
  81 }
  82
  83 #define XOR_ACC(src, r...)                                              \
  84 {                                                                       \
  85         switch (REG_CNT(r)) {                                           \
  86         case 4:                                                         \
  87                 __asm(                                                  \
  88                     "vpxor 0x00(%[SRC]), %%" VR0(r)", %%" VR0(r) "\n"   \
  89                     "vpxor 0x20(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n"   \
  90                     "vpxor 0x40(%[SRC]), %%" VR2(r)", %%" VR2(r) "\n"   \
  91                     "vpxor 0x60(%[SRC]), %%" VR3(r)", %%" VR3(r) "\n"   \
  92                     : : [SRC] "r" (src));                               \
  93                 break;                                                  \
  94         case 2:                                                         \
  95                 __asm(                                                  \
  96                     "vpxor 0x00(%[SRC]), %%" VR0(r)", %%" VR0(r) "\n"   \
  97                     "vpxor 0x20(%[SRC]), %%" VR1(r)", %%" VR1(r) "\n"   \
  98                     : : [SRC] "r" (src));                               \
  99                 break;                                                  \
 100         default:                                                        \
 101                 ASM_BUG();                                              \
 102         }                                                               \
 103 }
 104
 105 #define XOR(r...)                                                       \
 106 {                                                                       \
 107         switch (REG_CNT(r)) {                                           \
 108         case 8:                                                         \
 109                 __asm(                                                  \
 110                     "vpxor %" VR0(r) ", %" VR4(r)", %" VR4(r) "\n"      \
 111                     "vpxor %" VR1(r) ", %" VR5(r)", %" VR5(r) "\n"      \
 112                     "vpxor %" VR2(r) ", %" VR6(r)", %" VR6(r) "\n"      \
 113                     "vpxor %" VR3(r) ", %" VR7(r)", %" VR7(r));         \
 114                 break;                                                  \
 115         case 4:                                                         \
 116                 __asm(                                                  \
 117                     "vpxor %" VR0(r) ", %" VR2(r)", %" VR2(r) "\n"      \
 118                     "vpxor %" VR1(r) ", %" VR3(r)", %" VR3(r));         \
 119                 break;                                                  \
 120         default:                                                        \
 121                 ASM_BUG();                                              \
 122         }                                                               \
 123 }
 124
 125 #define ZERO(r...)                                                      \
 126 {                                                                       \
 127         switch (REG_CNT(r)) {                                           \
 128         case 4:                                                         \
 129                 __asm(                                                  \
 130                     "vpxor %" VR0(r) ", %" VR0(r)", %" VR0(r) "\n"      \
 131                     "vpxor %" VR1(r) ", %" VR1(r)", %" VR1(r) "\n"      \
 132                     "vpxor %" VR2(r) ", %" VR2(r)", %" VR2(r) "\n"      \
 133                     "vpxor %" VR3(r) ", %" VR3(r)", %" VR3(r));         \
 134                 break;                                                  \
 135         case 2:                                                         \
 136                 __asm(                                                  \
 137                     "vpxor %" VR0(r) ", %" VR0(r)", %" VR0(r) "\n"      \
 138                     "vpxor %" VR1(r) ", %" VR1(r)", %" VR1(r));         \
 139                 break;                                                  \
 140         default:                                                        \
 141                 ASM_BUG();                                              \
 142         }                                                               \
 143 }
 144
 145 #define COPY(r...)                                                      \
 146 {                                                                       \
 147         switch (REG_CNT(r)) {                                           \
 148         case 8:                                                         \
 149                 __asm(                                                  \
 150                     "vmovdqa %" VR0(r) ", %" VR4(r) "\n"                \
 151                     "vmovdqa %" VR1(r) ", %" VR5(r) "\n"                \
 152                     "vmovdqa %" VR2(r) ", %" VR6(r) "\n"                \
 153                     "vmovdqa %" VR3(r) ", %" VR7(r));                   \
 154                 break;                                                  \
 155         case 4:                                                         \
 156                 __asm(                                                  \
 157                     "vmovdqa %" VR0(r) ", %" VR2(r) "\n"                \
 158                     "vmovdqa %" VR1(r) ", %" VR3(r));                   \
 159                 break;                                                  \
 160         default:                                                        \
 161                 ASM_BUG();                                              \
 162         }                                                               \
 163 }
 164
 165 #define LOAD(src, r...)                                                 \
 166 {                                                                       \
 167         switch (REG_CNT(r)) {                                           \
 168         case 4:                                                         \
 169                 __asm(                                                  \
 170                     "vmovdqa 0x00(%[SRC]), %%" VR0(r) "\n"              \
 171                     "vmovdqa 0x20(%[SRC]), %%" VR1(r) "\n"              \
 172                     "vmovdqa 0x40(%[SRC]), %%" VR2(r) "\n"              \
 173                     "vmovdqa 0x60(%[SRC]), %%" VR3(r) "\n"              \
 174                     : : [SRC] "r" (src));                               \
 175                 break;                                                  \
 176         case 2:                                                         \
 177                 __asm(                                                  \
 178                     "vmovdqa 0x00(%[SRC]), %%" VR0(r) "\n"              \
 179                     "vmovdqa 0x20(%[SRC]), %%" VR1(r) "\n"              \
 180                     : : [SRC] "r" (src));                               \
 181                 break;                                                  \
 182         default:                                                        \
 183                 ASM_BUG();                                              \
 184         }                                                               \
 185 }
 186
 187 #define STORE(dst, r...)                                                \
 188 {                                                                       \
 189         switch (REG_CNT(r)) {                                           \
 190         case 4:                                                         \
 191                 __asm(                                                  \
 192                     "vmovdqa %%" VR0(r) ", 0x00(%[DST])\n"              \
 193                     "vmovdqa %%" VR1(r) ", 0x20(%[DST])\n"              \
 194                     "vmovdqa %%" VR2(r) ", 0x40(%[DST])\n"              \
 195                     "vmovdqa %%" VR3(r) ", 0x60(%[DST])\n"              \
 196                     : : [DST] "r" (dst));                               \
 197                 break;                                                  \
 198         case 2:                                                         \
 199                 __asm(                                                  \
 200                     "vmovdqa %%" VR0(r) ", 0x00(%[DST])\n"              \
 201                     "vmovdqa %%" VR1(r) ", 0x20(%[DST])\n"              \
 202                     : : [DST] "r" (dst));                               \
 203                 break;                                                  \
 204         default:                                                        \
 205                 ASM_BUG();                                              \
 206         }                                                               \
 207 }
 208
 209 #define FLUSH()                                                         \
 210 {                                                                       \
 211         __asm("vzeroupper");                                            \
 212 }
 213
 214 #define MUL2_SETUP()                                                    \
 215 {                                                                       \
 216         __asm("vmovq %0,   %%xmm14" :: "r"(0x1d1d1d1d1d1d1d1d));        \
 217         __asm("vpbroadcastq %xmm14, %ymm14");                           \
 218         __asm("vpxor        %ymm15, %ymm15 ,%ymm15");                   \
 219 }
 220
 221 #define _MUL2(r...)                                                     \
 222 {                                                                       \
 223         switch  (REG_CNT(r)) {                                          \
 224         case 2:                                                         \
 225                 __asm(                                                  \
 226                     "vpcmpgtb %" VR0(r)", %ymm15,     %ymm12\n"         \
 227                     "vpcmpgtb %" VR1(r)", %ymm15,     %ymm13\n"         \
 228                     "vpaddb   %" VR0(r)", %" VR0(r)", %" VR0(r) "\n"    \
 229                     "vpaddb   %" VR1(r)", %" VR1(r)", %" VR1(r) "\n"    \
 230                     "vpand    %ymm14,     %ymm12,     %ymm12\n"         \
 231                     "vpand    %ymm14,     %ymm13,     %ymm13\n"         \
 232                     "vpxor    %ymm12,     %" VR0(r)", %" VR0(r) "\n"    \
 233                     "vpxor    %ymm13,     %" VR1(r)", %" VR1(r));       \
 234                 break;                                                  \
 235         default:                                                        \
 236                 ASM_BUG();                                              \
 237         }                                                               \
 238 }
 239
 240 #define MUL2(r...)                                                      \
 241 {                                                                       \
 242         switch (REG_CNT(r)) {                                           \
 243         case 4:                                                         \
 244             _MUL2(R_01(r));                                             \
 245             _MUL2(R_23(r));                                             \
 246             break;                                                      \
 247         case 2:                                                         \
 248             _MUL2(r);                                                   \
 249             break;                                                      \
 250         default:                                                        \
 251                 ASM_BUG();                                              \
 252         }                                                               \
 253 }
 254
 255 #define MUL4(r...)                                                      \
 256 {                                                                       \
 257         MUL2(r);                                                        \
 258         MUL2(r);                                                        \
 259 }
 260
 261 #define _0f             "ymm15"
 262 #define _as             "ymm14"
 263 #define _bs             "ymm13"
 264 #define _ltmod          "ymm12"
 265 #define _ltmul          "ymm11"
 266 #define _ta             "ymm10"
 267 #define _tb             "ymm15"
 268
 269 static const uint8_t __attribute__((aligned(32))) _mul_mask = 0x0F;
 270
 271 #define _MULx2(c, r...)                                                 \
 272 {                                                                       \
 273         switch (REG_CNT(r)) {                                           \
 274         case 2:                                                         \
 275                 __asm(                                                  \
 276                     "vpbroadcastb (%[mask]), %%" _0f "\n"               \
 277                     /* upper bits */                                    \
 278                     "vbroadcasti128 0x00(%[lt]), %%" _ltmod "\n"        \
 279                     "vbroadcasti128 0x10(%[lt]), %%" _ltmul "\n"        \
 280                                                                         \
 281                     "vpsraw $0x4, %%" VR0(r) ", %%"_as "\n"             \
 282                     "vpsraw $0x4, %%" VR1(r) ", %%"_bs "\n"             \
 283                     "vpand %%" _0f ", %%" VR0(r) ", %%" VR0(r) "\n"     \
 284                     "vpand %%" _0f ", %%" VR1(r) ", %%" VR1(r) "\n"     \
 285                     "vpand %%" _0f ", %%" _as ", %%" _as "\n"           \
 286                     "vpand %%" _0f ", %%" _bs ", %%" _bs "\n"           \
 287                                                                         \
 288                     "vpshufb %%" _as ", %%" _ltmod ", %%" _ta "\n"      \
 289                     "vpshufb %%" _bs ", %%" _ltmod ", %%" _tb "\n"      \
 290                     "vpshufb %%" _as ", %%" _ltmul ", %%" _as "\n"      \
 291                     "vpshufb %%" _bs ", %%" _ltmul ", %%" _bs "\n"      \
 292                     /* lower bits */                                    \
 293                     "vbroadcasti128 0x20(%[lt]), %%" _ltmod "\n"        \
 294                     "vbroadcasti128 0x30(%[lt]), %%" _ltmul "\n"        \
 295                                                                         \
 296                     "vpxor %%" _ta ", %%" _as ", %%" _as "\n"           \
 297                     "vpxor %%" _tb ", %%" _bs ", %%" _bs "\n"           \
 298                                                                         \
 299                     "vpshufb %%" VR0(r) ", %%" _ltmod ", %%" _ta "\n"   \
 300                     "vpshufb %%" VR1(r) ", %%" _ltmod ", %%" _tb "\n"   \
 301                     "vpshufb %%" VR0(r) ", %%" _ltmul ", %%" VR0(r) "\n"\
 302                     "vpshufb %%" VR1(r) ", %%" _ltmul ", %%" VR1(r) "\n"\
 303                                                                         \
 304                     "vpxor %%" _ta ", %%" VR0(r) ", %%" VR0(r) "\n"     \
 305                     "vpxor %%" _as ", %%" VR0(r) ", %%" VR0(r) "\n"     \
 306                     "vpxor %%" _tb ", %%" VR1(r) ", %%" VR1(r) "\n"     \
 307                     "vpxor %%" _bs ", %%" VR1(r) ", %%" VR1(r) "\n"     \
 308                     : : [mask] "r" (&_mul_mask),                        \
 309                     [lt] "r" (gf_clmul_mod_lt[4*(c)]));                 \
 310                 break;                                                  \
 311         default:                                                        \
 312                 ASM_BUG();                                              \
 313         }                                                               \
 314 }
 315
 316 #define MUL(c, r...)                                                    \
 317 {                                                                       \
 318         switch (REG_CNT(r)) {                                           \
 319         case 4:                                                         \
 320                 _MULx2(c, R_01(r));                                     \
 321                 _MULx2(c, R_23(r));                                     \
 322                 break;                                                  \
 323         case 2:                                                         \
 324                 _MULx2(c, R_01(r));                                     \
 325                 break;                                                  \
 326         default:                                                        \
 327                 ASM_BUG();                                              \
 328         }                                                               \
 329 }
 330
 331 #define raidz_math_begin()      kfpu_begin()
 332 #define raidz_math_end()                                                \
 333 {                                                                       \
 334         FLUSH();                                                        \
 335         kfpu_end();                                                     \
 336 }
 337
 338 #define GEN_P_DEFINE()          {}
 339 #define GEN_P_STRIDE            4
 340 #define GEN_P_P                 0, 1, 2, 3
 341
 342 #define GEN_PQ_DEFINE()         {}
 343 #define GEN_PQ_STRIDE           4
 344 #define GEN_PQ_D                0, 1, 2, 3
 345 #define GEN_PQ_P                4, 5, 6, 7
 346 #define GEN_PQ_Q                8, 9, 10, 11
 347
 348 #define GEN_PQR_DEFINE()        {}
 349 #define GEN_PQR_STRIDE          2
 350 #define GEN_PQR_D               0, 1
 351 #define GEN_PQR_P               2, 3
 352 #define GEN_PQR_Q               4, 5
 353 #define GEN_PQR_R               6, 7
 354
 355 #define REC_P_DEFINE()          {}
 356 #define REC_P_STRIDE            4
 357 #define REC_P_X                 0, 1, 2, 3
 358
 359 #define REC_Q_DEFINE()          {}
 360 #define REC_Q_STRIDE            4
 361 #define REC_Q_X                 0, 1, 2, 3
 362
 363 #define REC_R_DEFINE()          {}
 364 #define REC_R_STRIDE            4
 365 #define REC_R_X                 0, 1, 2, 3
 366
 367 #define REC_PQ_DEFINE()         {}
 368 #define REC_PQ_STRIDE           2
 369 #define REC_PQ_X                0, 1
 370 #define REC_PQ_Y                2, 3
 371 #define REC_PQ_D                4, 5
 372
 373 #define REC_PR_DEFINE()         {}
 374 #define REC_PR_STRIDE           2
 375 #define REC_PR_X                0, 1
 376 #define REC_PR_Y                2, 3
 377 #define REC_PR_D                4, 5
 378
 379 #define REC_QR_DEFINE()         {}
 380 #define REC_QR_STRIDE           2
 381 #define REC_QR_X                0, 1
 382 #define REC_QR_Y                2, 3
 383 #define REC_QR_D                4, 5
 384
 385 #define REC_PQR_DEFINE()        {}
 386 #define REC_PQR_STRIDE          2
 387 #define REC_PQR_X               0, 1
 388 #define REC_PQR_Y               2, 3
 389 #define REC_PQR_Z               4, 5
 390 #define REC_PQR_D               6, 7
 391 #define REC_PQR_XS              6, 7
 392 #define REC_PQR_YS              8, 9
 393
 394
 395 #include <sys/vdev_raidz_impl.h>
 396 #include "vdev_raidz_math_impl.h"
 397
 398 DEFINE_GEN_METHODS(avx2);
 399 DEFINE_REC_METHODS(avx2);
 400
 401 static boolean_t
 402 raidz_will_avx2_work(void)
 403 {
 404         return (zfs_avx_available() && zfs_avx2_available());
 405 }
 406
 407 const raidz_impl_ops_t vdev_raidz_avx2_impl = {
 408         .init = NULL,
 409         .fini = NULL,
 410         .gen = RAIDZ_GEN_METHODS(avx2),
 411         .rec = RAIDZ_REC_METHODS(avx2),
 412         .is_supported = &raidz_will_avx2_work,
 413         .name = "avx2"
 414 };
 415
 416 #endif /* defined(__x86_64) && defined(HAVE_AVX2) */