2 #include "exec/gdbstub.h"
4 #include "qemu/host-utils.h"
5 #include "sysemu/sysemu.h"
6 #include "qemu/bitops.h"
8 #ifndef CONFIG_USER_ONLY
9 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
10 int access_type
, int is_user
,
11 hwaddr
*phys_ptr
, int *prot
,
12 target_ulong
*page_size
);
15 static int vfp_gdb_get_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
19 /* VFP data registers are always little-endian. */
20 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
22 stfq_le_p(buf
, env
->vfp
.regs
[reg
]);
25 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
26 /* Aliases for Q regs. */
29 stfq_le_p(buf
, env
->vfp
.regs
[(reg
- 32) * 2]);
30 stfq_le_p(buf
+ 8, env
->vfp
.regs
[(reg
- 32) * 2 + 1]);
34 switch (reg
- nregs
) {
35 case 0: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSID
]); return 4;
36 case 1: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPSCR
]); return 4;
37 case 2: stl_p(buf
, env
->vfp
.xregs
[ARM_VFP_FPEXC
]); return 4;
42 static int vfp_gdb_set_reg(CPUARMState
*env
, uint8_t *buf
, int reg
)
46 nregs
= arm_feature(env
, ARM_FEATURE_VFP3
) ? 32 : 16;
48 env
->vfp
.regs
[reg
] = ldfq_le_p(buf
);
51 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
54 env
->vfp
.regs
[(reg
- 32) * 2] = ldfq_le_p(buf
);
55 env
->vfp
.regs
[(reg
- 32) * 2 + 1] = ldfq_le_p(buf
+ 8);
59 switch (reg
- nregs
) {
60 case 0: env
->vfp
.xregs
[ARM_VFP_FPSID
] = ldl_p(buf
); return 4;
61 case 1: env
->vfp
.xregs
[ARM_VFP_FPSCR
] = ldl_p(buf
); return 4;
62 case 2: env
->vfp
.xregs
[ARM_VFP_FPEXC
] = ldl_p(buf
) & (1 << 30); return 4;
67 static int dacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
70 tlb_flush(env
, 1); /* Flush TLB as domain not tracked in TLB */
74 static int fcse_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
76 if (env
->cp15
.c13_fcse
!= value
) {
77 /* Unlike real hardware the qemu TLB uses virtual addresses,
78 * not modified virtual addresses, so this causes a TLB flush.
81 env
->cp15
.c13_fcse
= value
;
85 static int contextidr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
88 if (env
->cp15
.c13_context
!= value
&& !arm_feature(env
, ARM_FEATURE_MPU
)) {
89 /* For VMSA (when not using the LPAE long descriptor page table
90 * format) this register includes the ASID, so do a TLB flush.
91 * For PMSA it is purely a process ID and no action is needed.
95 env
->cp15
.c13_context
= value
;
99 static int tlbiall_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
102 /* Invalidate all (TLBIALL) */
107 static int tlbimva_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
110 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
111 tlb_flush_page(env
, value
& TARGET_PAGE_MASK
);
115 static int tlbiasid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
118 /* Invalidate by ASID (TLBIASID) */
119 tlb_flush(env
, value
== 0);
123 static int tlbimvaa_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
126 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
127 tlb_flush_page(env
, value
& TARGET_PAGE_MASK
);
131 static const ARMCPRegInfo cp_reginfo
[] = {
132 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
133 * version" bits will read as a reserved value, which should cause
134 * Linux to not try to use the debug hardware.
136 { .name
= "DBGDIDR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
137 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
138 /* MMU Domain access control / MPU write buffer control */
139 { .name
= "DACR", .cp
= 15,
140 .crn
= 3, .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
141 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c3
),
142 .resetvalue
= 0, .writefn
= dacr_write
},
143 { .name
= "FCSEIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 0,
144 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
145 .resetvalue
= 0, .writefn
= fcse_write
},
146 { .name
= "CONTEXTIDR", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 1,
147 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_fcse
),
148 .resetvalue
= 0, .writefn
= contextidr_write
},
149 /* ??? This covers not just the impdef TLB lockdown registers but also
150 * some v7VMSA registers relating to TEX remap, so it is overly broad.
152 { .name
= "TLB_LOCKDOWN", .cp
= 15, .crn
= 10, .crm
= CP_ANY
,
153 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_NOP
},
154 /* MMU TLB control. Note that the wildcarding means we cover not just
155 * the unified TLB ops but also the dside/iside/inner-shareable variants.
157 { .name
= "TLBIALL", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
158 .opc1
= CP_ANY
, .opc2
= 0, .access
= PL1_W
, .writefn
= tlbiall_write
, },
159 { .name
= "TLBIMVA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
160 .opc1
= CP_ANY
, .opc2
= 1, .access
= PL1_W
, .writefn
= tlbimva_write
, },
161 { .name
= "TLBIASID", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
162 .opc1
= CP_ANY
, .opc2
= 2, .access
= PL1_W
, .writefn
= tlbiasid_write
, },
163 { .name
= "TLBIMVAA", .cp
= 15, .crn
= 8, .crm
= CP_ANY
,
164 .opc1
= CP_ANY
, .opc2
= 3, .access
= PL1_W
, .writefn
= tlbimvaa_write
, },
165 /* Cache maintenance ops; some of this space may be overridden later. */
166 { .name
= "CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
167 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
,
168 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
},
172 static const ARMCPRegInfo not_v6_cp_reginfo
[] = {
173 /* Not all pre-v6 cores implemented this WFI, so this is slightly
176 { .name
= "WFI_v5", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= 2,
177 .access
= PL1_W
, .type
= ARM_CP_WFI
},
181 static const ARMCPRegInfo not_v7_cp_reginfo
[] = {
182 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
183 * is UNPREDICTABLE; we choose to NOP as most implementations do).
185 { .name
= "WFI_v6", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
186 .access
= PL1_W
, .type
= ARM_CP_WFI
},
187 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
188 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
189 * OMAPCP will override this space.
191 { .name
= "DLOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 0,
192 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_data
),
194 { .name
= "ILOCKDOWN", .cp
= 15, .crn
= 9, .crm
= 0, .opc1
= 0, .opc2
= 1,
195 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_insn
),
197 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
198 { .name
= "DUMMY", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= CP_ANY
,
199 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
203 static int cpacr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
205 if (env
->cp15
.c1_coproc
!= value
) {
206 env
->cp15
.c1_coproc
= value
;
207 /* ??? Is this safe when called from within a TB? */
213 static const ARMCPRegInfo v6_cp_reginfo
[] = {
214 /* prefetch by MVA in v6, NOP in v7 */
215 { .name
= "MVA_prefetch",
216 .cp
= 15, .crn
= 7, .crm
= 13, .opc1
= 0, .opc2
= 1,
217 .access
= PL1_W
, .type
= ARM_CP_NOP
},
218 { .name
= "ISB", .cp
= 15, .crn
= 7, .crm
= 5, .opc1
= 0, .opc2
= 4,
219 .access
= PL0_W
, .type
= ARM_CP_NOP
},
220 { .name
= "DSB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 4,
221 .access
= PL0_W
, .type
= ARM_CP_NOP
},
222 { .name
= "DMB", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 5,
223 .access
= PL0_W
, .type
= ARM_CP_NOP
},
224 { .name
= "IFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 2,
225 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_insn
),
227 /* Watchpoint Fault Address Register : should actually only be present
228 * for 1136, 1176, 11MPCore.
230 { .name
= "WFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 1,
231 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0, },
232 { .name
= "CPACR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 2,
233 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_coproc
),
234 .resetvalue
= 0, .writefn
= cpacr_write
},
238 static int pmreg_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
241 /* Generic performance monitor register read function for where
242 * user access may be allowed by PMUSERENR.
244 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
247 *value
= CPREG_FIELD32(env
, ri
);
251 static int pmcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
254 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
257 /* only the DP, X, D and E bits are writable */
258 env
->cp15
.c9_pmcr
&= ~0x39;
259 env
->cp15
.c9_pmcr
|= (value
& 0x39);
263 static int pmcntenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
266 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
270 env
->cp15
.c9_pmcnten
|= value
;
274 static int pmcntenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
277 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
281 env
->cp15
.c9_pmcnten
&= ~value
;
285 static int pmovsr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
288 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
291 env
->cp15
.c9_pmovsr
&= ~value
;
295 static int pmxevtyper_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
298 if (arm_current_pl(env
) == 0 && !env
->cp15
.c9_pmuserenr
) {
301 env
->cp15
.c9_pmxevtyper
= value
& 0xff;
305 static int pmuserenr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
308 env
->cp15
.c9_pmuserenr
= value
& 1;
312 static int pmintenset_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
315 /* We have no event counters so only the C bit can be changed */
317 env
->cp15
.c9_pminten
|= value
;
321 static int pmintenclr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
325 env
->cp15
.c9_pminten
&= ~value
;
329 static int ccsidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
332 ARMCPU
*cpu
= arm_env_get_cpu(env
);
333 *value
= cpu
->ccsidr
[env
->cp15
.c0_cssel
];
337 static int csselr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
340 env
->cp15
.c0_cssel
= value
& 0xf;
344 static const ARMCPRegInfo v7_cp_reginfo
[] = {
345 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
348 { .name
= "DBGDRAR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
349 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
350 { .name
= "DBGDSAR", .cp
= 14, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
351 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
352 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
353 { .name
= "NOP", .cp
= 15, .crn
= 7, .crm
= 0, .opc1
= 0, .opc2
= 4,
354 .access
= PL1_W
, .type
= ARM_CP_NOP
},
355 /* Performance monitors are implementation defined in v7,
356 * but with an ARM recommended set of registers, which we
357 * follow (although we don't actually implement any counters)
359 * Performance registers fall into three categories:
360 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
361 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
362 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
363 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
364 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
366 { .name
= "PMCNTENSET", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 1,
367 .access
= PL0_RW
, .resetvalue
= 0,
368 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
369 .readfn
= pmreg_read
, .writefn
= pmcntenset_write
},
370 { .name
= "PMCNTENCLR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 2,
371 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcnten
),
372 .readfn
= pmreg_read
, .writefn
= pmcntenclr_write
},
373 { .name
= "PMOVSR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 3,
374 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmovsr
),
375 .readfn
= pmreg_read
, .writefn
= pmovsr_write
},
376 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
379 { .name
= "PMSWINC", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 4,
380 .access
= PL0_W
, .type
= ARM_CP_NOP
},
381 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
382 * We choose to RAZ/WI. XXX should respect PMUSERENR.
384 { .name
= "PMSELR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 5,
385 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
386 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
387 { .name
= "PMCCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 0,
388 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
389 { .name
= "PMXEVTYPER", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 1,
391 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmxevtyper
),
392 .readfn
= pmreg_read
, .writefn
= pmxevtyper_write
},
393 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
394 { .name
= "PMXEVCNTR", .cp
= 15, .crn
= 9, .crm
= 13, .opc1
= 0, .opc2
= 2,
395 .access
= PL0_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
396 { .name
= "PMUSERENR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 0,
397 .access
= PL0_R
| PL1_RW
,
398 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmuserenr
),
400 .writefn
= pmuserenr_write
},
401 { .name
= "PMINTENSET", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 1,
403 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
405 .writefn
= pmintenset_write
},
406 { .name
= "PMINTENCLR", .cp
= 15, .crn
= 9, .crm
= 14, .opc1
= 0, .opc2
= 2,
408 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pminten
),
410 .writefn
= pmintenclr_write
},
411 { .name
= "SCR", .cp
= 15, .crn
= 1, .crm
= 1, .opc1
= 0, .opc2
= 0,
412 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_scr
),
414 { .name
= "CCSIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 0,
415 .access
= PL1_R
, .readfn
= ccsidr_read
},
416 { .name
= "CSSELR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 2, .opc2
= 0,
417 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cssel
),
418 .writefn
= csselr_write
, .resetvalue
= 0 },
419 /* Auxiliary ID register: this actually has an IMPDEF value but for now
420 * just RAZ for all cores:
422 { .name
= "AIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 7,
423 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
427 static int teecr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
434 static int teehbr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
437 /* This is a helper function because the user access rights
438 * depend on the value of the TEECR.
440 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
443 *value
= env
->teehbr
;
447 static int teehbr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
450 if (arm_current_pl(env
) == 0 && (env
->teecr
& 1)) {
457 static const ARMCPRegInfo t2ee_cp_reginfo
[] = {
458 { .name
= "TEECR", .cp
= 14, .crn
= 0, .crm
= 0, .opc1
= 6, .opc2
= 0,
459 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, teecr
),
461 .writefn
= teecr_write
},
462 { .name
= "TEEHBR", .cp
= 14, .crn
= 1, .crm
= 0, .opc1
= 6, .opc2
= 0,
463 .access
= PL0_RW
, .fieldoffset
= offsetof(CPUARMState
, teehbr
),
465 .readfn
= teehbr_read
, .writefn
= teehbr_write
},
469 static const ARMCPRegInfo v6k_cp_reginfo
[] = {
470 { .name
= "TPIDRURW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 2,
472 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls1
),
474 { .name
= "TPIDRURO", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 3,
475 .access
= PL0_R
|PL1_W
,
476 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls2
),
478 { .name
= "TPIDRPRW", .cp
= 15, .crn
= 13, .crm
= 0, .opc1
= 0, .opc2
= 4,
480 .fieldoffset
= offsetof(CPUARMState
, cp15
.c13_tls3
),
485 static const ARMCPRegInfo generic_timer_cp_reginfo
[] = {
486 /* Dummy implementation: RAZ/WI the whole crn=14 space */
487 { .name
= "GENERIC_TIMER", .cp
= 15, .crn
= 14,
488 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
489 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
493 static int par_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
495 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
496 env
->cp15
.c7_par
= value
;
497 } else if (arm_feature(env
, ARM_FEATURE_V7
)) {
498 env
->cp15
.c7_par
= value
& 0xfffff6ff;
500 env
->cp15
.c7_par
= value
& 0xfffff1ff;
505 #ifndef CONFIG_USER_ONLY
506 /* get_phys_addr() isn't present for user-mode-only targets */
508 /* Return true if extended addresses are enabled, ie this is an
509 * LPAE implementation and we are using the long-descriptor translation
510 * table format because the TTBCR EAE bit is set.
512 static inline bool extended_addresses_enabled(CPUARMState
*env
)
514 return arm_feature(env
, ARM_FEATURE_LPAE
)
515 && (env
->cp15
.c2_control
& (1 << 31));
518 static int ats_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
521 target_ulong page_size
;
523 int ret
, is_user
= ri
->opc2
& 2;
524 int access_type
= ri
->opc2
& 1;
527 /* Other states are only available with TrustZone */
530 ret
= get_phys_addr(env
, value
, access_type
, is_user
,
531 &phys_addr
, &prot
, &page_size
);
532 if (extended_addresses_enabled(env
)) {
533 /* ret is a DFSR/IFSR value for the long descriptor
534 * translation table format, but with WnR always clear.
535 * Convert it to a 64-bit PAR.
537 uint64_t par64
= (1 << 11); /* LPAE bit always set */
539 par64
|= phys_addr
& ~0xfffULL
;
540 /* We don't set the ATTR or SH fields in the PAR. */
543 par64
|= (ret
& 0x3f) << 1; /* FS */
544 /* Note that S2WLK and FSTAGE are always zero, because we don't
545 * implement virtualization and therefore there can't be a stage 2
549 env
->cp15
.c7_par
= par64
;
550 env
->cp15
.c7_par_hi
= par64
>> 32;
552 /* ret is a DFSR/IFSR value for the short descriptor
553 * translation table format (with WnR always clear).
554 * Convert it to a 32-bit PAR.
557 /* We do not set any attribute bits in the PAR */
558 if (page_size
== (1 << 24)
559 && arm_feature(env
, ARM_FEATURE_V7
)) {
560 env
->cp15
.c7_par
= (phys_addr
& 0xff000000) | 1 << 1;
562 env
->cp15
.c7_par
= phys_addr
& 0xfffff000;
565 env
->cp15
.c7_par
= ((ret
& (10 << 1)) >> 5) |
566 ((ret
& (12 << 1)) >> 6) |
567 ((ret
& 0xf) << 1) | 1;
569 env
->cp15
.c7_par_hi
= 0;
575 static const ARMCPRegInfo vapa_cp_reginfo
[] = {
576 { .name
= "PAR", .cp
= 15, .crn
= 7, .crm
= 4, .opc1
= 0, .opc2
= 0,
577 .access
= PL1_RW
, .resetvalue
= 0,
578 .fieldoffset
= offsetof(CPUARMState
, cp15
.c7_par
),
579 .writefn
= par_write
},
580 #ifndef CONFIG_USER_ONLY
581 { .name
= "ATS", .cp
= 15, .crn
= 7, .crm
= 8, .opc1
= 0, .opc2
= CP_ANY
,
582 .access
= PL1_W
, .writefn
= ats_write
},
587 /* Return basic MPU access permission bits. */
588 static uint32_t simple_mpu_ap_bits(uint32_t val
)
595 for (i
= 0; i
< 16; i
+= 2) {
596 ret
|= (val
>> i
) & mask
;
602 /* Pad basic MPU access permission bits to extended format. */
603 static uint32_t extended_mpu_ap_bits(uint32_t val
)
610 for (i
= 0; i
< 16; i
+= 2) {
611 ret
|= (val
& mask
) << i
;
617 static int pmsav5_data_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
620 env
->cp15
.c5_data
= extended_mpu_ap_bits(value
);
624 static int pmsav5_data_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
627 *value
= simple_mpu_ap_bits(env
->cp15
.c5_data
);
631 static int pmsav5_insn_ap_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
634 env
->cp15
.c5_insn
= extended_mpu_ap_bits(value
);
638 static int pmsav5_insn_ap_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
641 *value
= simple_mpu_ap_bits(env
->cp15
.c5_insn
);
645 static int arm946_prbs_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
651 *value
= env
->cp15
.c6_region
[ri
->crm
];
655 static int arm946_prbs_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
661 env
->cp15
.c6_region
[ri
->crm
] = value
;
665 static const ARMCPRegInfo pmsav5_cp_reginfo
[] = {
666 { .name
= "DATA_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
668 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0,
669 .readfn
= pmsav5_data_ap_read
, .writefn
= pmsav5_data_ap_write
, },
670 { .name
= "INSN_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
672 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0,
673 .readfn
= pmsav5_insn_ap_read
, .writefn
= pmsav5_insn_ap_write
, },
674 { .name
= "DATA_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 2,
676 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
677 { .name
= "INSN_EXT_AP", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 3,
679 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
680 { .name
= "DCACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
682 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_data
), .resetvalue
= 0, },
683 { .name
= "ICACHE_CFG", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
685 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_insn
), .resetvalue
= 0, },
686 /* Protection region base and size registers */
687 { .name
= "946_PRBS", .cp
= 15, .crn
= 6, .crm
= CP_ANY
, .opc1
= 0,
688 .opc2
= CP_ANY
, .access
= PL1_RW
,
689 .readfn
= arm946_prbs_read
, .writefn
= arm946_prbs_write
, },
693 static int vmsa_ttbcr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
696 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
697 value
&= ~((7 << 19) | (3 << 14) | (0xf << 3));
698 /* With LPAE the TTBCR could result in a change of ASID
699 * via the TTBCR.A1 bit, so do a TLB flush.
705 /* Note that we always calculate c2_mask and c2_base_mask, but
706 * they are only used for short-descriptor tables (ie if EAE is 0);
707 * for long-descriptor tables the TTBCR fields are used differently
708 * and the c2_mask and c2_base_mask values are meaningless.
710 env
->cp15
.c2_control
= value
;
711 env
->cp15
.c2_mask
= ~(((uint32_t)0xffffffffu
) >> value
);
712 env
->cp15
.c2_base_mask
= ~((uint32_t)0x3fffu
>> value
);
716 static void vmsa_ttbcr_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
718 env
->cp15
.c2_base_mask
= 0xffffc000u
;
719 env
->cp15
.c2_control
= 0;
720 env
->cp15
.c2_mask
= 0;
723 static const ARMCPRegInfo vmsa_cp_reginfo
[] = {
724 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 0,
726 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
727 { .name
= "IFSR", .cp
= 15, .crn
= 5, .crm
= 0, .opc1
= 0, .opc2
= 1,
729 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_insn
), .resetvalue
= 0, },
730 { .name
= "TTBR0", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 0,
732 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base0
), .resetvalue
= 0, },
733 { .name
= "TTBR1", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 1,
735 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_base1
), .resetvalue
= 0, },
736 { .name
= "TTBCR", .cp
= 15, .crn
= 2, .crm
= 0, .opc1
= 0, .opc2
= 2,
737 .access
= PL1_RW
, .writefn
= vmsa_ttbcr_write
,
738 .resetfn
= vmsa_ttbcr_reset
,
739 .fieldoffset
= offsetof(CPUARMState
, cp15
.c2_control
) },
740 { .name
= "DFAR", .cp
= 15, .crn
= 6, .crm
= 0, .opc1
= 0, .opc2
= 0,
741 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c6_data
),
746 static int omap_ticonfig_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
749 env
->cp15
.c15_ticonfig
= value
& 0xe7;
750 /* The OS_TYPE bit in this register changes the reported CPUID! */
751 env
->cp15
.c0_cpuid
= (value
& (1 << 5)) ?
752 ARM_CPUID_TI915T
: ARM_CPUID_TI925T
;
756 static int omap_threadid_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
759 env
->cp15
.c15_threadid
= value
& 0xffff;
763 static int omap_wfi_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
766 /* Wait-for-interrupt (deprecated) */
767 cpu_interrupt(env
, CPU_INTERRUPT_HALT
);
771 static int omap_cachemaint_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
774 /* On OMAP there are registers indicating the max/min index of dcache lines
775 * containing a dirty line; cache flush operations have to reset these.
777 env
->cp15
.c15_i_max
= 0x000;
778 env
->cp15
.c15_i_min
= 0xff0;
782 static const ARMCPRegInfo omap_cp_reginfo
[] = {
783 { .name
= "DFSR", .cp
= 15, .crn
= 5, .crm
= CP_ANY
,
784 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
, .type
= ARM_CP_OVERRIDE
,
785 .fieldoffset
= offsetof(CPUARMState
, cp15
.c5_data
), .resetvalue
= 0, },
786 { .name
= "", .cp
= 15, .crn
= 15, .crm
= 0, .opc1
= 0, .opc2
= 0,
787 .access
= PL1_RW
, .type
= ARM_CP_NOP
},
788 { .name
= "TICONFIG", .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0,
790 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_ticonfig
), .resetvalue
= 0,
791 .writefn
= omap_ticonfig_write
},
792 { .name
= "IMAX", .cp
= 15, .crn
= 15, .crm
= 2, .opc1
= 0, .opc2
= 0,
794 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_max
), .resetvalue
= 0, },
795 { .name
= "IMIN", .cp
= 15, .crn
= 15, .crm
= 3, .opc1
= 0, .opc2
= 0,
796 .access
= PL1_RW
, .resetvalue
= 0xff0,
797 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_i_min
) },
798 { .name
= "THREADID", .cp
= 15, .crn
= 15, .crm
= 4, .opc1
= 0, .opc2
= 0,
800 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_threadid
), .resetvalue
= 0,
801 .writefn
= omap_threadid_write
},
802 { .name
= "TI925T_STATUS", .cp
= 15, .crn
= 15,
803 .crm
= 8, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
804 .readfn
= arm_cp_read_zero
, .writefn
= omap_wfi_write
, },
805 /* TODO: Peripheral port remap register:
806 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
807 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
810 { .name
= "OMAP_CACHEMAINT", .cp
= 15, .crn
= 7, .crm
= CP_ANY
,
811 .opc1
= 0, .opc2
= CP_ANY
, .access
= PL1_W
, .type
= ARM_CP_OVERRIDE
,
812 .writefn
= omap_cachemaint_write
},
813 { .name
= "C9", .cp
= 15, .crn
= 9,
814 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_RW
,
815 .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
, .resetvalue
= 0 },
819 static int xscale_cpar_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
823 if (env
->cp15
.c15_cpar
!= value
) {
824 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
826 env
->cp15
.c15_cpar
= value
;
831 static const ARMCPRegInfo xscale_cp_reginfo
[] = {
832 { .name
= "XSCALE_CPAR",
833 .cp
= 15, .crn
= 15, .crm
= 1, .opc1
= 0, .opc2
= 0, .access
= PL1_RW
,
834 .fieldoffset
= offsetof(CPUARMState
, cp15
.c15_cpar
), .resetvalue
= 0,
835 .writefn
= xscale_cpar_write
, },
836 { .name
= "XSCALE_AUXCR",
837 .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1, .access
= PL1_RW
,
838 .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_xscaleauxcr
),
843 static const ARMCPRegInfo dummy_c15_cp_reginfo
[] = {
844 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
845 * implementation of this implementation-defined space.
846 * Ideally this should eventually disappear in favour of actually
847 * implementing the correct behaviour for all cores.
849 { .name
= "C15_IMPDEF", .cp
= 15, .crn
= 15,
850 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
851 .access
= PL1_RW
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
855 static const ARMCPRegInfo cache_dirty_status_cp_reginfo
[] = {
856 /* Cache status: RAZ because we have no cache so it's always clean */
857 { .name
= "CDSR", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 6,
858 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
862 static const ARMCPRegInfo cache_block_ops_cp_reginfo
[] = {
863 /* We never have a a block transfer operation in progress */
864 { .name
= "BXSR", .cp
= 15, .crn
= 7, .crm
= 12, .opc1
= 0, .opc2
= 4,
865 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
866 /* The cache ops themselves: these all NOP for QEMU */
867 { .name
= "IICR", .cp
= 15, .crm
= 5, .opc1
= 0,
868 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
869 { .name
= "IDCR", .cp
= 15, .crm
= 6, .opc1
= 0,
870 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
871 { .name
= "CDCR", .cp
= 15, .crm
= 12, .opc1
= 0,
872 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
873 { .name
= "PIR", .cp
= 15, .crm
= 12, .opc1
= 1,
874 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
875 { .name
= "PDR", .cp
= 15, .crm
= 12, .opc1
= 2,
876 .access
= PL0_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
877 { .name
= "CIDCR", .cp
= 15, .crm
= 14, .opc1
= 0,
878 .access
= PL1_W
, .type
= ARM_CP_NOP
|ARM_CP_64BIT
},
882 static const ARMCPRegInfo cache_test_clean_cp_reginfo
[] = {
883 /* The cache test-and-clean instructions always return (1 << 30)
884 * to indicate that there are no dirty cache lines.
886 { .name
= "TC_DCACHE", .cp
= 15, .crn
= 7, .crm
= 10, .opc1
= 0, .opc2
= 3,
887 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= (1 << 30) },
888 { .name
= "TCI_DCACHE", .cp
= 15, .crn
= 7, .crm
= 14, .opc1
= 0, .opc2
= 3,
889 .access
= PL0_R
, .type
= ARM_CP_CONST
, .resetvalue
= (1 << 30) },
893 static const ARMCPRegInfo strongarm_cp_reginfo
[] = {
894 /* Ignore ReadBuffer accesses */
895 { .name
= "C9_READBUFFER", .cp
= 15, .crn
= 9,
896 .crm
= CP_ANY
, .opc1
= CP_ANY
, .opc2
= CP_ANY
,
897 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
,
902 static int mpidr_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
905 CPUState
*cs
= CPU(arm_env_get_cpu(env
));
906 uint32_t mpidr
= cs
->cpu_index
;
907 /* We don't support setting cluster ID ([8..11])
908 * so these bits always RAZ.
910 if (arm_feature(env
, ARM_FEATURE_V7MP
)) {
912 /* Cores which are uniprocessor (non-coherent)
913 * but still implement the MP extensions set
914 * bit 30. (For instance, A9UP.) However we do
915 * not currently model any of those cores.
922 static const ARMCPRegInfo mpidr_cp_reginfo
[] = {
923 { .name
= "MPIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 5,
924 .access
= PL1_R
, .readfn
= mpidr_read
},
928 static int par64_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t *value
)
930 *value
= ((uint64_t)env
->cp15
.c7_par_hi
<< 32) | env
->cp15
.c7_par
;
934 static int par64_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
936 env
->cp15
.c7_par_hi
= value
>> 32;
937 env
->cp15
.c7_par
= value
;
941 static void par64_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
943 env
->cp15
.c7_par_hi
= 0;
944 env
->cp15
.c7_par
= 0;
947 static int ttbr064_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
950 *value
= ((uint64_t)env
->cp15
.c2_base0_hi
<< 32) | env
->cp15
.c2_base0
;
954 static int ttbr064_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
957 env
->cp15
.c2_base0_hi
= value
>> 32;
958 env
->cp15
.c2_base0
= value
;
959 /* Writes to the 64 bit format TTBRs may change the ASID */
964 static void ttbr064_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
966 env
->cp15
.c2_base0_hi
= 0;
967 env
->cp15
.c2_base0
= 0;
970 static int ttbr164_read(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
973 *value
= ((uint64_t)env
->cp15
.c2_base1_hi
<< 32) | env
->cp15
.c2_base1
;
977 static int ttbr164_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
980 env
->cp15
.c2_base1_hi
= value
>> 32;
981 env
->cp15
.c2_base1
= value
;
985 static void ttbr164_reset(CPUARMState
*env
, const ARMCPRegInfo
*ri
)
987 env
->cp15
.c2_base1_hi
= 0;
988 env
->cp15
.c2_base1
= 0;
991 static const ARMCPRegInfo lpae_cp_reginfo
[] = {
992 /* NOP AMAIR0/1: the override is because these clash with the rather
993 * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
995 { .name
= "AMAIR0", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 0,
996 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
,
998 { .name
= "AMAIR1", .cp
= 15, .crn
= 10, .crm
= 3, .opc1
= 0, .opc2
= 1,
999 .access
= PL1_RW
, .type
= ARM_CP_CONST
| ARM_CP_OVERRIDE
,
1001 /* 64 bit access versions of the (dummy) debug registers */
1002 { .name
= "DBGDRAR", .cp
= 14, .crm
= 1, .opc1
= 0,
1003 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
1004 { .name
= "DBGDSAR", .cp
= 14, .crm
= 2, .opc1
= 0,
1005 .access
= PL0_R
, .type
= ARM_CP_CONST
|ARM_CP_64BIT
, .resetvalue
= 0 },
1006 { .name
= "PAR", .cp
= 15, .crm
= 7, .opc1
= 0,
1007 .access
= PL1_RW
, .type
= ARM_CP_64BIT
,
1008 .readfn
= par64_read
, .writefn
= par64_write
, .resetfn
= par64_reset
},
1009 { .name
= "TTBR0", .cp
= 15, .crm
= 2, .opc1
= 0,
1010 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .readfn
= ttbr064_read
,
1011 .writefn
= ttbr064_write
, .resetfn
= ttbr064_reset
},
1012 { .name
= "TTBR1", .cp
= 15, .crm
= 2, .opc1
= 1,
1013 .access
= PL1_RW
, .type
= ARM_CP_64BIT
, .readfn
= ttbr164_read
,
1014 .writefn
= ttbr164_write
, .resetfn
= ttbr164_reset
},
1018 static int sctlr_write(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t value
)
1020 env
->cp15
.c1_sys
= value
;
1021 /* ??? Lots of these bits are not implemented. */
1022 /* This may enable/disable the MMU, so do a TLB flush. */
1027 void register_cp_regs_for_features(ARMCPU
*cpu
)
1029 /* Register all the coprocessor registers based on feature bits */
1030 CPUARMState
*env
= &cpu
->env
;
1031 if (arm_feature(env
, ARM_FEATURE_M
)) {
1032 /* M profile has no coprocessor registers */
1036 define_arm_cp_regs(cpu
, cp_reginfo
);
1037 if (arm_feature(env
, ARM_FEATURE_V6
)) {
1038 /* The ID registers all have impdef reset values */
1039 ARMCPRegInfo v6_idregs
[] = {
1040 { .name
= "ID_PFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1041 .opc1
= 0, .opc2
= 0, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1042 .resetvalue
= cpu
->id_pfr0
},
1043 { .name
= "ID_PFR1", .cp
= 15, .crn
= 0, .crm
= 1,
1044 .opc1
= 0, .opc2
= 1, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1045 .resetvalue
= cpu
->id_pfr1
},
1046 { .name
= "ID_DFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1047 .opc1
= 0, .opc2
= 2, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1048 .resetvalue
= cpu
->id_dfr0
},
1049 { .name
= "ID_AFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1050 .opc1
= 0, .opc2
= 3, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1051 .resetvalue
= cpu
->id_afr0
},
1052 { .name
= "ID_MMFR0", .cp
= 15, .crn
= 0, .crm
= 1,
1053 .opc1
= 0, .opc2
= 4, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1054 .resetvalue
= cpu
->id_mmfr0
},
1055 { .name
= "ID_MMFR1", .cp
= 15, .crn
= 0, .crm
= 1,
1056 .opc1
= 0, .opc2
= 5, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1057 .resetvalue
= cpu
->id_mmfr1
},
1058 { .name
= "ID_MMFR2", .cp
= 15, .crn
= 0, .crm
= 1,
1059 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1060 .resetvalue
= cpu
->id_mmfr2
},
1061 { .name
= "ID_MMFR3", .cp
= 15, .crn
= 0, .crm
= 1,
1062 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1063 .resetvalue
= cpu
->id_mmfr3
},
1064 { .name
= "ID_ISAR0", .cp
= 15, .crn
= 0, .crm
= 2,
1065 .opc1
= 0, .opc2
= 0, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1066 .resetvalue
= cpu
->id_isar0
},
1067 { .name
= "ID_ISAR1", .cp
= 15, .crn
= 0, .crm
= 2,
1068 .opc1
= 0, .opc2
= 1, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1069 .resetvalue
= cpu
->id_isar1
},
1070 { .name
= "ID_ISAR2", .cp
= 15, .crn
= 0, .crm
= 2,
1071 .opc1
= 0, .opc2
= 2, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1072 .resetvalue
= cpu
->id_isar2
},
1073 { .name
= "ID_ISAR3", .cp
= 15, .crn
= 0, .crm
= 2,
1074 .opc1
= 0, .opc2
= 3, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1075 .resetvalue
= cpu
->id_isar3
},
1076 { .name
= "ID_ISAR4", .cp
= 15, .crn
= 0, .crm
= 2,
1077 .opc1
= 0, .opc2
= 4, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1078 .resetvalue
= cpu
->id_isar4
},
1079 { .name
= "ID_ISAR5", .cp
= 15, .crn
= 0, .crm
= 2,
1080 .opc1
= 0, .opc2
= 5, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1081 .resetvalue
= cpu
->id_isar5
},
1082 /* 6..7 are as yet unallocated and must RAZ */
1083 { .name
= "ID_ISAR6", .cp
= 15, .crn
= 0, .crm
= 2,
1084 .opc1
= 0, .opc2
= 6, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1086 { .name
= "ID_ISAR7", .cp
= 15, .crn
= 0, .crm
= 2,
1087 .opc1
= 0, .opc2
= 7, .access
= PL1_R
, .type
= ARM_CP_CONST
,
1091 define_arm_cp_regs(cpu
, v6_idregs
);
1092 define_arm_cp_regs(cpu
, v6_cp_reginfo
);
1094 define_arm_cp_regs(cpu
, not_v6_cp_reginfo
);
1096 if (arm_feature(env
, ARM_FEATURE_V6K
)) {
1097 define_arm_cp_regs(cpu
, v6k_cp_reginfo
);
1099 if (arm_feature(env
, ARM_FEATURE_V7
)) {
1100 /* v7 performance monitor control register: same implementor
1101 * field as main ID register, and we implement no event counters.
1103 ARMCPRegInfo pmcr
= {
1104 .name
= "PMCR", .cp
= 15, .crn
= 9, .crm
= 12, .opc1
= 0, .opc2
= 0,
1105 .access
= PL0_RW
, .resetvalue
= cpu
->midr
& 0xff000000,
1106 .fieldoffset
= offsetof(CPUARMState
, cp15
.c9_pmcr
),
1107 .readfn
= pmreg_read
, .writefn
= pmcr_write
1109 ARMCPRegInfo clidr
= {
1110 .name
= "CLIDR", .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 1, .opc2
= 1,
1111 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->clidr
1113 define_one_arm_cp_reg(cpu
, &pmcr
);
1114 define_one_arm_cp_reg(cpu
, &clidr
);
1115 define_arm_cp_regs(cpu
, v7_cp_reginfo
);
1117 define_arm_cp_regs(cpu
, not_v7_cp_reginfo
);
1119 if (arm_feature(env
, ARM_FEATURE_MPU
)) {
1120 /* These are the MPU registers prior to PMSAv6. Any new
1121 * PMSA core later than the ARM946 will require that we
1122 * implement the PMSAv6 or PMSAv7 registers, which are
1123 * completely different.
1125 assert(!arm_feature(env
, ARM_FEATURE_V6
));
1126 define_arm_cp_regs(cpu
, pmsav5_cp_reginfo
);
1128 define_arm_cp_regs(cpu
, vmsa_cp_reginfo
);
1130 if (arm_feature(env
, ARM_FEATURE_THUMB2EE
)) {
1131 define_arm_cp_regs(cpu
, t2ee_cp_reginfo
);
1133 if (arm_feature(env
, ARM_FEATURE_GENERIC_TIMER
)) {
1134 define_arm_cp_regs(cpu
, generic_timer_cp_reginfo
);
1136 if (arm_feature(env
, ARM_FEATURE_VAPA
)) {
1137 define_arm_cp_regs(cpu
, vapa_cp_reginfo
);
1139 if (arm_feature(env
, ARM_FEATURE_CACHE_TEST_CLEAN
)) {
1140 define_arm_cp_regs(cpu
, cache_test_clean_cp_reginfo
);
1142 if (arm_feature(env
, ARM_FEATURE_CACHE_DIRTY_REG
)) {
1143 define_arm_cp_regs(cpu
, cache_dirty_status_cp_reginfo
);
1145 if (arm_feature(env
, ARM_FEATURE_CACHE_BLOCK_OPS
)) {
1146 define_arm_cp_regs(cpu
, cache_block_ops_cp_reginfo
);
1148 if (arm_feature(env
, ARM_FEATURE_OMAPCP
)) {
1149 define_arm_cp_regs(cpu
, omap_cp_reginfo
);
1151 if (arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
1152 define_arm_cp_regs(cpu
, strongarm_cp_reginfo
);
1154 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1155 define_arm_cp_regs(cpu
, xscale_cp_reginfo
);
1157 if (arm_feature(env
, ARM_FEATURE_DUMMY_C15_REGS
)) {
1158 define_arm_cp_regs(cpu
, dummy_c15_cp_reginfo
);
1160 if (arm_feature(env
, ARM_FEATURE_MPIDR
)) {
1161 define_arm_cp_regs(cpu
, mpidr_cp_reginfo
);
1163 if (arm_feature(env
, ARM_FEATURE_LPAE
)) {
1164 define_arm_cp_regs(cpu
, lpae_cp_reginfo
);
1166 /* Slightly awkwardly, the OMAP and StrongARM cores need all of
1167 * cp15 crn=0 to be writes-ignored, whereas for other cores they should
1168 * be read-only (ie write causes UNDEF exception).
1171 ARMCPRegInfo id_cp_reginfo
[] = {
1172 /* Note that the MIDR isn't a simple constant register because
1173 * of the TI925 behaviour where writes to another register can
1174 * cause the MIDR value to change.
1177 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 0,
1178 .access
= PL1_R
, .resetvalue
= cpu
->midr
,
1179 .writefn
= arm_cp_write_ignore
,
1180 .fieldoffset
= offsetof(CPUARMState
, cp15
.c0_cpuid
) },
1182 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 1,
1183 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= cpu
->ctr
},
1185 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 2,
1186 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1188 .cp
= 15, .crn
= 0, .crm
= 0, .opc1
= 0, .opc2
= 3,
1189 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1190 /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
1192 .cp
= 15, .crn
= 0, .crm
= 3, .opc1
= 0, .opc2
= CP_ANY
,
1193 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1195 .cp
= 15, .crn
= 0, .crm
= 4, .opc1
= 0, .opc2
= CP_ANY
,
1196 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1198 .cp
= 15, .crn
= 0, .crm
= 5, .opc1
= 0, .opc2
= CP_ANY
,
1199 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1201 .cp
= 15, .crn
= 0, .crm
= 6, .opc1
= 0, .opc2
= CP_ANY
,
1202 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1204 .cp
= 15, .crn
= 0, .crm
= 7, .opc1
= 0, .opc2
= CP_ANY
,
1205 .access
= PL1_R
, .type
= ARM_CP_CONST
, .resetvalue
= 0 },
1208 ARMCPRegInfo crn0_wi_reginfo
= {
1209 .name
= "CRN0_WI", .cp
= 15, .crn
= 0, .crm
= CP_ANY
,
1210 .opc1
= CP_ANY
, .opc2
= CP_ANY
, .access
= PL1_W
,
1211 .type
= ARM_CP_NOP
| ARM_CP_OVERRIDE
1213 if (arm_feature(env
, ARM_FEATURE_OMAPCP
) ||
1214 arm_feature(env
, ARM_FEATURE_STRONGARM
)) {
1216 /* Register the blanket "writes ignored" value first to cover the
1217 * whole space. Then define the specific ID registers, but update
1218 * their access field to allow write access, so that they ignore
1219 * writes rather than causing them to UNDEF.
1221 define_one_arm_cp_reg(cpu
, &crn0_wi_reginfo
);
1222 for (r
= id_cp_reginfo
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
1224 define_one_arm_cp_reg(cpu
, r
);
1227 /* Just register the standard ID registers (read-only, meaning
1228 * that writes will UNDEF).
1230 define_arm_cp_regs(cpu
, id_cp_reginfo
);
1234 if (arm_feature(env
, ARM_FEATURE_AUXCR
)) {
1235 ARMCPRegInfo auxcr
= {
1236 .name
= "AUXCR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 1,
1237 .access
= PL1_RW
, .type
= ARM_CP_CONST
,
1238 .resetvalue
= cpu
->reset_auxcr
1240 define_one_arm_cp_reg(cpu
, &auxcr
);
1243 /* Generic registers whose values depend on the implementation */
1245 ARMCPRegInfo sctlr
= {
1246 .name
= "SCTLR", .cp
= 15, .crn
= 1, .crm
= 0, .opc1
= 0, .opc2
= 0,
1247 .access
= PL1_RW
, .fieldoffset
= offsetof(CPUARMState
, cp15
.c1_sys
),
1248 .writefn
= sctlr_write
, .resetvalue
= cpu
->reset_sctlr
1250 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
1251 /* Normally we would always end the TB on an SCTLR write, but Linux
1252 * arch/arm/mach-pxa/sleep.S expects two instructions following
1253 * an MMU enable to execute from cache. Imitate this behaviour.
1255 sctlr
.type
|= ARM_CP_SUPPRESS_TB_END
;
1257 define_one_arm_cp_reg(cpu
, &sctlr
);
1261 ARMCPU
*cpu_arm_init(const char *cpu_model
)
1266 static int inited
= 0;
1268 oc
= cpu_class_by_name(TYPE_ARM_CPU
, cpu_model
);
1272 cpu
= ARM_CPU(object_new(object_class_get_name(oc
)));
1274 env
->cpu_model_str
= cpu_model
;
1276 /* TODO this should be set centrally, once possible */
1277 object_property_set_bool(OBJECT(cpu
), true, "realized", NULL
);
1279 if (tcg_enabled() && !inited
) {
1281 arm_translate_init();
1287 void arm_cpu_register_gdb_regs_for_features(ARMCPU
*cpu
)
1289 CPUARMState
*env
= &cpu
->env
;
1291 if (arm_feature(env
, ARM_FEATURE_NEON
)) {
1292 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
1293 51, "arm-neon.xml", 0);
1294 } else if (arm_feature(env
, ARM_FEATURE_VFP3
)) {
1295 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
1296 35, "arm-vfp3.xml", 0);
1297 } else if (arm_feature(env
, ARM_FEATURE_VFP
)) {
1298 gdb_register_coprocessor(env
, vfp_gdb_get_reg
, vfp_gdb_set_reg
,
1299 19, "arm-vfp.xml", 0);
1303 /* Sort alphabetically by type name, except for "any". */
1304 static gint
arm_cpu_list_compare(gconstpointer a
, gconstpointer b
)
1306 ObjectClass
*class_a
= (ObjectClass
*)a
;
1307 ObjectClass
*class_b
= (ObjectClass
*)b
;
1308 const char *name_a
, *name_b
;
1310 name_a
= object_class_get_name(class_a
);
1311 name_b
= object_class_get_name(class_b
);
1312 if (strcmp(name_a
, "any-" TYPE_ARM_CPU
) == 0) {
1314 } else if (strcmp(name_b
, "any-" TYPE_ARM_CPU
) == 0) {
1317 return strcmp(name_a
, name_b
);
1321 static void arm_cpu_list_entry(gpointer data
, gpointer user_data
)
1323 ObjectClass
*oc
= data
;
1324 CPUListState
*s
= user_data
;
1325 const char *typename
;
1328 typename
= object_class_get_name(oc
);
1329 name
= g_strndup(typename
, strlen(typename
) - strlen("-" TYPE_ARM_CPU
));
1330 (*s
->cpu_fprintf
)(s
->file
, " %s\n",
1335 void arm_cpu_list(FILE *f
, fprintf_function cpu_fprintf
)
1339 .cpu_fprintf
= cpu_fprintf
,
1343 list
= object_class_get_list(TYPE_ARM_CPU
, false);
1344 list
= g_slist_sort(list
, arm_cpu_list_compare
);
1345 (*cpu_fprintf
)(f
, "Available CPUs:\n");
1346 g_slist_foreach(list
, arm_cpu_list_entry
, &s
);
1350 void define_one_arm_cp_reg_with_opaque(ARMCPU
*cpu
,
1351 const ARMCPRegInfo
*r
, void *opaque
)
1353 /* Define implementations of coprocessor registers.
1354 * We store these in a hashtable because typically
1355 * there are less than 150 registers in a space which
1356 * is 16*16*16*8*8 = 262144 in size.
1357 * Wildcarding is supported for the crm, opc1 and opc2 fields.
1358 * If a register is defined twice then the second definition is
1359 * used, so this can be used to define some generic registers and
1360 * then override them with implementation specific variations.
1361 * At least one of the original and the second definition should
1362 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
1363 * against accidental use.
1365 int crm
, opc1
, opc2
;
1366 int crmmin
= (r
->crm
== CP_ANY
) ? 0 : r
->crm
;
1367 int crmmax
= (r
->crm
== CP_ANY
) ? 15 : r
->crm
;
1368 int opc1min
= (r
->opc1
== CP_ANY
) ? 0 : r
->opc1
;
1369 int opc1max
= (r
->opc1
== CP_ANY
) ? 7 : r
->opc1
;
1370 int opc2min
= (r
->opc2
== CP_ANY
) ? 0 : r
->opc2
;
1371 int opc2max
= (r
->opc2
== CP_ANY
) ? 7 : r
->opc2
;
1372 /* 64 bit registers have only CRm and Opc1 fields */
1373 assert(!((r
->type
& ARM_CP_64BIT
) && (r
->opc2
|| r
->crn
)));
1374 /* Check that the register definition has enough info to handle
1375 * reads and writes if they are permitted.
1377 if (!(r
->type
& (ARM_CP_SPECIAL
|ARM_CP_CONST
))) {
1378 if (r
->access
& PL3_R
) {
1379 assert(r
->fieldoffset
|| r
->readfn
);
1381 if (r
->access
& PL3_W
) {
1382 assert(r
->fieldoffset
|| r
->writefn
);
1385 /* Bad type field probably means missing sentinel at end of reg list */
1386 assert(cptype_valid(r
->type
));
1387 for (crm
= crmmin
; crm
<= crmmax
; crm
++) {
1388 for (opc1
= opc1min
; opc1
<= opc1max
; opc1
++) {
1389 for (opc2
= opc2min
; opc2
<= opc2max
; opc2
++) {
1390 uint32_t *key
= g_new(uint32_t, 1);
1391 ARMCPRegInfo
*r2
= g_memdup(r
, sizeof(ARMCPRegInfo
));
1392 int is64
= (r
->type
& ARM_CP_64BIT
) ? 1 : 0;
1393 *key
= ENCODE_CP_REG(r
->cp
, is64
, r
->crn
, crm
, opc1
, opc2
);
1394 r2
->opaque
= opaque
;
1395 /* Make sure reginfo passed to helpers for wildcarded regs
1396 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
1401 /* Overriding of an existing definition must be explicitly
1404 if (!(r
->type
& ARM_CP_OVERRIDE
)) {
1405 ARMCPRegInfo
*oldreg
;
1406 oldreg
= g_hash_table_lookup(cpu
->cp_regs
, key
);
1407 if (oldreg
&& !(oldreg
->type
& ARM_CP_OVERRIDE
)) {
1408 fprintf(stderr
, "Register redefined: cp=%d %d bit "
1409 "crn=%d crm=%d opc1=%d opc2=%d, "
1410 "was %s, now %s\n", r2
->cp
, 32 + 32 * is64
,
1411 r2
->crn
, r2
->crm
, r2
->opc1
, r2
->opc2
,
1412 oldreg
->name
, r2
->name
);
1416 g_hash_table_insert(cpu
->cp_regs
, key
, r2
);
1422 void define_arm_cp_regs_with_opaque(ARMCPU
*cpu
,
1423 const ARMCPRegInfo
*regs
, void *opaque
)
1425 /* Define a whole list of registers */
1426 const ARMCPRegInfo
*r
;
1427 for (r
= regs
; r
->type
!= ARM_CP_SENTINEL
; r
++) {
1428 define_one_arm_cp_reg_with_opaque(cpu
, r
, opaque
);
1432 const ARMCPRegInfo
*get_arm_cp_reginfo(ARMCPU
*cpu
, uint32_t encoded_cp
)
1434 return g_hash_table_lookup(cpu
->cp_regs
, &encoded_cp
);
1437 int arm_cp_write_ignore(CPUARMState
*env
, const ARMCPRegInfo
*ri
,
1440 /* Helper coprocessor write function for write-ignore registers */
1444 int arm_cp_read_zero(CPUARMState
*env
, const ARMCPRegInfo
*ri
, uint64_t *value
)
1446 /* Helper coprocessor write function for read-as-zero registers */
1451 static int bad_mode_switch(CPUARMState
*env
, int mode
)
1453 /* Return true if it is not valid for us to switch to
1454 * this CPU mode (ie all the UNPREDICTABLE cases in
1455 * the ARM ARM CPSRWriteByInstr pseudocode).
1458 case ARM_CPU_MODE_USR
:
1459 case ARM_CPU_MODE_SYS
:
1460 case ARM_CPU_MODE_SVC
:
1461 case ARM_CPU_MODE_ABT
:
1462 case ARM_CPU_MODE_UND
:
1463 case ARM_CPU_MODE_IRQ
:
1464 case ARM_CPU_MODE_FIQ
:
1471 uint32_t cpsr_read(CPUARMState
*env
)
1474 ZF
= (env
->ZF
== 0);
1475 return env
->uncached_cpsr
| (env
->NF
& 0x80000000) | (ZF
<< 30) |
1476 (env
->CF
<< 29) | ((env
->VF
& 0x80000000) >> 3) | (env
->QF
<< 27)
1477 | (env
->thumb
<< 5) | ((env
->condexec_bits
& 3) << 25)
1478 | ((env
->condexec_bits
& 0xfc) << 8)
1482 void cpsr_write(CPUARMState
*env
, uint32_t val
, uint32_t mask
)
1484 if (mask
& CPSR_NZCV
) {
1485 env
->ZF
= (~val
) & CPSR_Z
;
1487 env
->CF
= (val
>> 29) & 1;
1488 env
->VF
= (val
<< 3) & 0x80000000;
1491 env
->QF
= ((val
& CPSR_Q
) != 0);
1493 env
->thumb
= ((val
& CPSR_T
) != 0);
1494 if (mask
& CPSR_IT_0_1
) {
1495 env
->condexec_bits
&= ~3;
1496 env
->condexec_bits
|= (val
>> 25) & 3;
1498 if (mask
& CPSR_IT_2_7
) {
1499 env
->condexec_bits
&= 3;
1500 env
->condexec_bits
|= (val
>> 8) & 0xfc;
1502 if (mask
& CPSR_GE
) {
1503 env
->GE
= (val
>> 16) & 0xf;
1506 if ((env
->uncached_cpsr
^ val
) & mask
& CPSR_M
) {
1507 if (bad_mode_switch(env
, val
& CPSR_M
)) {
1508 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
1509 * We choose to ignore the attempt and leave the CPSR M field
1514 switch_mode(env
, val
& CPSR_M
);
1517 mask
&= ~CACHED_CPSR_BITS
;
1518 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~mask
) | (val
& mask
);
1521 /* Sign/zero extend */
1522 uint32_t HELPER(sxtb16
)(uint32_t x
)
1525 res
= (uint16_t)(int8_t)x
;
1526 res
|= (uint32_t)(int8_t)(x
>> 16) << 16;
1530 uint32_t HELPER(uxtb16
)(uint32_t x
)
1533 res
= (uint16_t)(uint8_t)x
;
1534 res
|= (uint32_t)(uint8_t)(x
>> 16) << 16;
1538 uint32_t HELPER(clz
)(uint32_t x
)
1543 int32_t HELPER(sdiv
)(int32_t num
, int32_t den
)
1547 if (num
== INT_MIN
&& den
== -1)
1552 uint32_t HELPER(udiv
)(uint32_t num
, uint32_t den
)
1559 uint32_t HELPER(rbit
)(uint32_t x
)
1561 x
= ((x
& 0xff000000) >> 24)
1562 | ((x
& 0x00ff0000) >> 8)
1563 | ((x
& 0x0000ff00) << 8)
1564 | ((x
& 0x000000ff) << 24);
1565 x
= ((x
& 0xf0f0f0f0) >> 4)
1566 | ((x
& 0x0f0f0f0f) << 4);
1567 x
= ((x
& 0x88888888) >> 3)
1568 | ((x
& 0x44444444) >> 1)
1569 | ((x
& 0x22222222) << 1)
1570 | ((x
& 0x11111111) << 3);
1574 #if defined(CONFIG_USER_ONLY)
1576 void do_interrupt (CPUARMState
*env
)
1578 env
->exception_index
= -1;
1581 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
, int rw
,
1585 env
->exception_index
= EXCP_PREFETCH_ABORT
;
1586 env
->cp15
.c6_insn
= address
;
1588 env
->exception_index
= EXCP_DATA_ABORT
;
1589 env
->cp15
.c6_data
= address
;
1594 /* These should probably raise undefined insn exceptions. */
1595 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
1597 cpu_abort(env
, "v7m_mrs %d\n", reg
);
1600 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
1602 cpu_abort(env
, "v7m_mrs %d\n", reg
);
1606 void switch_mode(CPUARMState
*env
, int mode
)
1608 if (mode
!= ARM_CPU_MODE_USR
)
1609 cpu_abort(env
, "Tried to switch out of user mode\n");
1612 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
1614 cpu_abort(env
, "banked r13 write\n");
1617 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
1619 cpu_abort(env
, "banked r13 read\n");
1625 /* Map CPU modes onto saved register banks. */
1626 static inline int bank_number(CPUARMState
*env
, int mode
)
1629 case ARM_CPU_MODE_USR
:
1630 case ARM_CPU_MODE_SYS
:
1632 case ARM_CPU_MODE_SVC
:
1634 case ARM_CPU_MODE_ABT
:
1636 case ARM_CPU_MODE_UND
:
1638 case ARM_CPU_MODE_IRQ
:
1640 case ARM_CPU_MODE_FIQ
:
1643 cpu_abort(env
, "Bad mode %x\n", mode
);
1647 void switch_mode(CPUARMState
*env
, int mode
)
1652 old_mode
= env
->uncached_cpsr
& CPSR_M
;
1653 if (mode
== old_mode
)
1656 if (old_mode
== ARM_CPU_MODE_FIQ
) {
1657 memcpy (env
->fiq_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
1658 memcpy (env
->regs
+ 8, env
->usr_regs
, 5 * sizeof(uint32_t));
1659 } else if (mode
== ARM_CPU_MODE_FIQ
) {
1660 memcpy (env
->usr_regs
, env
->regs
+ 8, 5 * sizeof(uint32_t));
1661 memcpy (env
->regs
+ 8, env
->fiq_regs
, 5 * sizeof(uint32_t));
1664 i
= bank_number(env
, old_mode
);
1665 env
->banked_r13
[i
] = env
->regs
[13];
1666 env
->banked_r14
[i
] = env
->regs
[14];
1667 env
->banked_spsr
[i
] = env
->spsr
;
1669 i
= bank_number(env
, mode
);
1670 env
->regs
[13] = env
->banked_r13
[i
];
1671 env
->regs
[14] = env
->banked_r14
[i
];
1672 env
->spsr
= env
->banked_spsr
[i
];
1675 static void v7m_push(CPUARMState
*env
, uint32_t val
)
1678 stl_phys(env
->regs
[13], val
);
1681 static uint32_t v7m_pop(CPUARMState
*env
)
1684 val
= ldl_phys(env
->regs
[13]);
1689 /* Switch to V7M main or process stack pointer. */
1690 static void switch_v7m_sp(CPUARMState
*env
, int process
)
1693 if (env
->v7m
.current_sp
!= process
) {
1694 tmp
= env
->v7m
.other_sp
;
1695 env
->v7m
.other_sp
= env
->regs
[13];
1696 env
->regs
[13] = tmp
;
1697 env
->v7m
.current_sp
= process
;
1701 static void do_v7m_exception_exit(CPUARMState
*env
)
1706 type
= env
->regs
[15];
1707 if (env
->v7m
.exception
!= 0)
1708 armv7m_nvic_complete_irq(env
->nvic
, env
->v7m
.exception
);
1710 /* Switch to the target stack. */
1711 switch_v7m_sp(env
, (type
& 4) != 0);
1712 /* Pop registers. */
1713 env
->regs
[0] = v7m_pop(env
);
1714 env
->regs
[1] = v7m_pop(env
);
1715 env
->regs
[2] = v7m_pop(env
);
1716 env
->regs
[3] = v7m_pop(env
);
1717 env
->regs
[12] = v7m_pop(env
);
1718 env
->regs
[14] = v7m_pop(env
);
1719 env
->regs
[15] = v7m_pop(env
);
1720 xpsr
= v7m_pop(env
);
1721 xpsr_write(env
, xpsr
, 0xfffffdff);
1722 /* Undo stack alignment. */
1725 /* ??? The exception return type specifies Thread/Handler mode. However
1726 this is also implied by the xPSR value. Not sure what to do
1727 if there is a mismatch. */
1728 /* ??? Likewise for mismatches between the CONTROL register and the stack
1732 static void do_interrupt_v7m(CPUARMState
*env
)
1734 uint32_t xpsr
= xpsr_read(env
);
1739 if (env
->v7m
.current_sp
)
1741 if (env
->v7m
.exception
== 0)
1744 /* For exceptions we just mark as pending on the NVIC, and let that
1746 /* TODO: Need to escalate if the current priority is higher than the
1747 one we're raising. */
1748 switch (env
->exception_index
) {
1750 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_USAGE
);
1753 /* The PC already points to the next instruction. */
1754 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_SVC
);
1756 case EXCP_PREFETCH_ABORT
:
1757 case EXCP_DATA_ABORT
:
1758 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_MEM
);
1761 if (semihosting_enabled
) {
1763 nr
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
1766 env
->regs
[0] = do_arm_semihosting(env
);
1770 armv7m_nvic_set_pending(env
->nvic
, ARMV7M_EXCP_DEBUG
);
1773 env
->v7m
.exception
= armv7m_nvic_acknowledge_irq(env
->nvic
);
1775 case EXCP_EXCEPTION_EXIT
:
1776 do_v7m_exception_exit(env
);
1779 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
1780 return; /* Never happens. Keep compiler happy. */
1783 /* Align stack pointer. */
1784 /* ??? Should only do this if Configuration Control Register
1785 STACKALIGN bit is set. */
1786 if (env
->regs
[13] & 4) {
1790 /* Switch to the handler mode. */
1791 v7m_push(env
, xpsr
);
1792 v7m_push(env
, env
->regs
[15]);
1793 v7m_push(env
, env
->regs
[14]);
1794 v7m_push(env
, env
->regs
[12]);
1795 v7m_push(env
, env
->regs
[3]);
1796 v7m_push(env
, env
->regs
[2]);
1797 v7m_push(env
, env
->regs
[1]);
1798 v7m_push(env
, env
->regs
[0]);
1799 switch_v7m_sp(env
, 0);
1801 env
->condexec_bits
= 0;
1803 addr
= ldl_phys(env
->v7m
.vecbase
+ env
->v7m
.exception
* 4);
1804 env
->regs
[15] = addr
& 0xfffffffe;
1805 env
->thumb
= addr
& 1;
1808 /* Handle a CPU exception. */
1809 void do_interrupt(CPUARMState
*env
)
1817 do_interrupt_v7m(env
);
1820 /* TODO: Vectored interrupt controller. */
1821 switch (env
->exception_index
) {
1823 new_mode
= ARM_CPU_MODE_UND
;
1832 if (semihosting_enabled
) {
1833 /* Check for semihosting interrupt. */
1835 mask
= arm_lduw_code(env
, env
->regs
[15] - 2, env
->bswap_code
)
1838 mask
= arm_ldl_code(env
, env
->regs
[15] - 4, env
->bswap_code
)
1841 /* Only intercept calls from privileged modes, to provide some
1842 semblance of security. */
1843 if (((mask
== 0x123456 && !env
->thumb
)
1844 || (mask
== 0xab && env
->thumb
))
1845 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
1846 env
->regs
[0] = do_arm_semihosting(env
);
1850 new_mode
= ARM_CPU_MODE_SVC
;
1853 /* The PC already points to the next instruction. */
1857 /* See if this is a semihosting syscall. */
1858 if (env
->thumb
&& semihosting_enabled
) {
1859 mask
= arm_lduw_code(env
, env
->regs
[15], env
->bswap_code
) & 0xff;
1861 && (env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
) {
1863 env
->regs
[0] = do_arm_semihosting(env
);
1867 env
->cp15
.c5_insn
= 2;
1868 /* Fall through to prefetch abort. */
1869 case EXCP_PREFETCH_ABORT
:
1870 new_mode
= ARM_CPU_MODE_ABT
;
1872 mask
= CPSR_A
| CPSR_I
;
1875 case EXCP_DATA_ABORT
:
1876 new_mode
= ARM_CPU_MODE_ABT
;
1878 mask
= CPSR_A
| CPSR_I
;
1882 new_mode
= ARM_CPU_MODE_IRQ
;
1884 /* Disable IRQ and imprecise data aborts. */
1885 mask
= CPSR_A
| CPSR_I
;
1889 new_mode
= ARM_CPU_MODE_FIQ
;
1891 /* Disable FIQ, IRQ and imprecise data aborts. */
1892 mask
= CPSR_A
| CPSR_I
| CPSR_F
;
1896 cpu_abort(env
, "Unhandled exception 0x%x\n", env
->exception_index
);
1897 return; /* Never happens. Keep compiler happy. */
1900 if (env
->cp15
.c1_sys
& (1 << 13)) {
1903 switch_mode (env
, new_mode
);
1904 env
->spsr
= cpsr_read(env
);
1905 /* Clear IT bits. */
1906 env
->condexec_bits
= 0;
1907 /* Switch to the new mode, and to the correct instruction set. */
1908 env
->uncached_cpsr
= (env
->uncached_cpsr
& ~CPSR_M
) | new_mode
;
1909 env
->uncached_cpsr
|= mask
;
1910 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
1911 * and we should just guard the thumb mode on V4 */
1912 if (arm_feature(env
, ARM_FEATURE_V4T
)) {
1913 env
->thumb
= (env
->cp15
.c1_sys
& (1 << 30)) != 0;
1915 env
->regs
[14] = env
->regs
[15] + offset
;
1916 env
->regs
[15] = addr
;
1917 env
->interrupt_request
|= CPU_INTERRUPT_EXITTB
;
1920 /* Check section/page access permissions.
1921 Returns the page protection flags, or zero if the access is not
1923 static inline int check_ap(CPUARMState
*env
, int ap
, int domain_prot
,
1924 int access_type
, int is_user
)
1928 if (domain_prot
== 3) {
1929 return PAGE_READ
| PAGE_WRITE
;
1932 if (access_type
== 1)
1935 prot_ro
= PAGE_READ
;
1939 if (access_type
== 1)
1941 switch ((env
->cp15
.c1_sys
>> 8) & 3) {
1943 return is_user
? 0 : PAGE_READ
;
1950 return is_user
? 0 : PAGE_READ
| PAGE_WRITE
;
1955 return PAGE_READ
| PAGE_WRITE
;
1957 return PAGE_READ
| PAGE_WRITE
;
1958 case 4: /* Reserved. */
1961 return is_user
? 0 : prot_ro
;
1965 if (!arm_feature (env
, ARM_FEATURE_V6K
))
1973 static uint32_t get_level1_table_address(CPUARMState
*env
, uint32_t address
)
1977 if (address
& env
->cp15
.c2_mask
)
1978 table
= env
->cp15
.c2_base1
& 0xffffc000;
1980 table
= env
->cp15
.c2_base0
& env
->cp15
.c2_base_mask
;
1982 table
|= (address
>> 18) & 0x3ffc;
1986 static int get_phys_addr_v5(CPUARMState
*env
, uint32_t address
, int access_type
,
1987 int is_user
, hwaddr
*phys_ptr
,
1988 int *prot
, target_ulong
*page_size
)
1999 /* Pagetable walk. */
2000 /* Lookup l1 descriptor. */
2001 table
= get_level1_table_address(env
, address
);
2002 desc
= ldl_phys(table
);
2004 domain
= (desc
>> 5) & 0x0f;
2005 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
2007 /* Section translation fault. */
2011 if (domain_prot
== 0 || domain_prot
== 2) {
2013 code
= 9; /* Section domain fault. */
2015 code
= 11; /* Page domain fault. */
2020 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
2021 ap
= (desc
>> 10) & 3;
2023 *page_size
= 1024 * 1024;
2025 /* Lookup l2 entry. */
2027 /* Coarse pagetable. */
2028 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
2030 /* Fine pagetable. */
2031 table
= (desc
& 0xfffff000) | ((address
>> 8) & 0xffc);
2033 desc
= ldl_phys(table
);
2035 case 0: /* Page translation fault. */
2038 case 1: /* 64k page. */
2039 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
2040 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
2041 *page_size
= 0x10000;
2043 case 2: /* 4k page. */
2044 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
2045 ap
= (desc
>> (4 + ((address
>> 13) & 6))) & 3;
2046 *page_size
= 0x1000;
2048 case 3: /* 1k page. */
2050 if (arm_feature(env
, ARM_FEATURE_XSCALE
)) {
2051 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
2053 /* Page translation fault. */
2058 phys_addr
= (desc
& 0xfffffc00) | (address
& 0x3ff);
2060 ap
= (desc
>> 4) & 3;
2064 /* Never happens, but compiler isn't smart enough to tell. */
2069 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
2071 /* Access permission fault. */
2075 *phys_ptr
= phys_addr
;
2078 return code
| (domain
<< 4);
2081 static int get_phys_addr_v6(CPUARMState
*env
, uint32_t address
, int access_type
,
2082 int is_user
, hwaddr
*phys_ptr
,
2083 int *prot
, target_ulong
*page_size
)
2096 /* Pagetable walk. */
2097 /* Lookup l1 descriptor. */
2098 table
= get_level1_table_address(env
, address
);
2099 desc
= ldl_phys(table
);
2101 if (type
== 0 || (type
== 3 && !arm_feature(env
, ARM_FEATURE_PXN
))) {
2102 /* Section translation fault, or attempt to use the encoding
2103 * which is Reserved on implementations without PXN.
2108 if ((type
== 1) || !(desc
& (1 << 18))) {
2109 /* Page or Section. */
2110 domain
= (desc
>> 5) & 0x0f;
2112 domain_prot
= (env
->cp15
.c3
>> (domain
* 2)) & 3;
2113 if (domain_prot
== 0 || domain_prot
== 2) {
2115 code
= 9; /* Section domain fault. */
2117 code
= 11; /* Page domain fault. */
2122 if (desc
& (1 << 18)) {
2124 phys_addr
= (desc
& 0xff000000) | (address
& 0x00ffffff);
2125 *page_size
= 0x1000000;
2128 phys_addr
= (desc
& 0xfff00000) | (address
& 0x000fffff);
2129 *page_size
= 0x100000;
2131 ap
= ((desc
>> 10) & 3) | ((desc
>> 13) & 4);
2132 xn
= desc
& (1 << 4);
2136 if (arm_feature(env
, ARM_FEATURE_PXN
)) {
2137 pxn
= (desc
>> 2) & 1;
2139 /* Lookup l2 entry. */
2140 table
= (desc
& 0xfffffc00) | ((address
>> 10) & 0x3fc);
2141 desc
= ldl_phys(table
);
2142 ap
= ((desc
>> 4) & 3) | ((desc
>> 7) & 4);
2144 case 0: /* Page translation fault. */
2147 case 1: /* 64k page. */
2148 phys_addr
= (desc
& 0xffff0000) | (address
& 0xffff);
2149 xn
= desc
& (1 << 15);
2150 *page_size
= 0x10000;
2152 case 2: case 3: /* 4k page. */
2153 phys_addr
= (desc
& 0xfffff000) | (address
& 0xfff);
2155 *page_size
= 0x1000;
2158 /* Never happens, but compiler isn't smart enough to tell. */
2163 if (domain_prot
== 3) {
2164 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2166 if (pxn
&& !is_user
) {
2169 if (xn
&& access_type
== 2)
2172 /* The simplified model uses AP[0] as an access control bit. */
2173 if ((env
->cp15
.c1_sys
& (1 << 29)) && (ap
& 1) == 0) {
2174 /* Access flag fault. */
2175 code
= (code
== 15) ? 6 : 3;
2178 *prot
= check_ap(env
, ap
, domain_prot
, access_type
, is_user
);
2180 /* Access permission fault. */
2187 *phys_ptr
= phys_addr
;
2190 return code
| (domain
<< 4);
2193 /* Fault type for long-descriptor MMU fault reporting; this corresponds
2194 * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
2197 translation_fault
= 1,
2199 permission_fault
= 3,
2202 static int get_phys_addr_lpae(CPUARMState
*env
, uint32_t address
,
2203 int access_type
, int is_user
,
2204 hwaddr
*phys_ptr
, int *prot
,
2205 target_ulong
*page_size_ptr
)
2207 /* Read an LPAE long-descriptor translation table. */
2208 MMUFaultType fault_type
= translation_fault
;
2216 uint32_t tableattrs
;
2217 target_ulong page_size
;
2220 /* Determine whether this address is in the region controlled by
2221 * TTBR0 or TTBR1 (or if it is in neither region and should fault).
2222 * This is a Non-secure PL0/1 stage 1 translation, so controlled by
2223 * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
2225 uint32_t t0sz
= extract32(env
->cp15
.c2_control
, 0, 3);
2226 uint32_t t1sz
= extract32(env
->cp15
.c2_control
, 16, 3);
2227 if (t0sz
&& !extract32(address
, 32 - t0sz
, t0sz
)) {
2228 /* there is a ttbr0 region and we are in it (high bits all zero) */
2230 } else if (t1sz
&& !extract32(~address
, 32 - t1sz
, t1sz
)) {
2231 /* there is a ttbr1 region and we are in it (high bits all one) */
2234 /* ttbr0 region is "everything not in the ttbr1 region" */
2237 /* ttbr1 region is "everything not in the ttbr0 region" */
2240 /* in the gap between the two regions, this is a Translation fault */
2241 fault_type
= translation_fault
;
2245 /* Note that QEMU ignores shareability and cacheability attributes,
2246 * so we don't need to do anything with the SH, ORGN, IRGN fields
2247 * in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
2248 * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
2249 * implement any ASID-like capability so we can ignore it (instead
2250 * we will always flush the TLB any time the ASID is changed).
2252 if (ttbr_select
== 0) {
2253 ttbr
= ((uint64_t)env
->cp15
.c2_base0_hi
<< 32) | env
->cp15
.c2_base0
;
2254 epd
= extract32(env
->cp15
.c2_control
, 7, 1);
2257 ttbr
= ((uint64_t)env
->cp15
.c2_base1_hi
<< 32) | env
->cp15
.c2_base1
;
2258 epd
= extract32(env
->cp15
.c2_control
, 23, 1);
2263 /* Translation table walk disabled => Translation fault on TLB miss */
2267 /* If the region is small enough we will skip straight to a 2nd level
2268 * lookup. This affects the number of bits of the address used in
2269 * combination with the TTBR to find the first descriptor. ('n' here
2270 * matches the usage in the ARM ARM sB3.6.6, where bits [39..n] are
2271 * from the TTBR, [n-1..3] from the vaddr, and [2..0] always zero).
2280 /* Clear the vaddr bits which aren't part of the within-region address,
2281 * so that we don't have to special case things when calculating the
2282 * first descriptor address.
2284 address
&= (0xffffffffU
>> tsz
);
2286 /* Now we can extract the actual base address from the TTBR */
2287 descaddr
= extract64(ttbr
, 0, 40);
2288 descaddr
&= ~((1ULL << n
) - 1);
2292 uint64_t descriptor
;
2294 descaddr
|= ((address
>> (9 * (4 - level
))) & 0xff8);
2295 descriptor
= ldq_phys(descaddr
);
2296 if (!(descriptor
& 1) ||
2297 (!(descriptor
& 2) && (level
== 3))) {
2298 /* Invalid, or the Reserved level 3 encoding */
2301 descaddr
= descriptor
& 0xfffffff000ULL
;
2303 if ((descriptor
& 2) && (level
< 3)) {
2304 /* Table entry. The top five bits are attributes which may
2305 * propagate down through lower levels of the table (and
2306 * which are all arranged so that 0 means "no effect", so
2307 * we can gather them up by ORing in the bits at each level).
2309 tableattrs
|= extract64(descriptor
, 59, 5);
2313 /* Block entry at level 1 or 2, or page entry at level 3.
2314 * These are basically the same thing, although the number
2315 * of bits we pull in from the vaddr varies.
2317 page_size
= (1 << (39 - (9 * level
)));
2318 descaddr
|= (address
& (page_size
- 1));
2319 /* Extract attributes from the descriptor and merge with table attrs */
2320 attrs
= extract64(descriptor
, 2, 10)
2321 | (extract64(descriptor
, 52, 12) << 10);
2322 attrs
|= extract32(tableattrs
, 0, 2) << 11; /* XN, PXN */
2323 attrs
|= extract32(tableattrs
, 3, 1) << 5; /* APTable[1] => AP[2] */
2324 /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
2325 * means "force PL1 access only", which means forcing AP[1] to 0.
2327 if (extract32(tableattrs
, 2, 1)) {
2330 /* Since we're always in the Non-secure state, NSTable is ignored. */
2333 /* Here descaddr is the final physical address, and attributes
2336 fault_type
= access_fault
;
2337 if ((attrs
& (1 << 8)) == 0) {
2341 fault_type
= permission_fault
;
2342 if (is_user
&& !(attrs
& (1 << 4))) {
2343 /* Unprivileged access not enabled */
2346 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2347 if (attrs
& (1 << 12) || (!is_user
&& (attrs
& (1 << 11)))) {
2349 if (access_type
== 2) {
2352 *prot
&= ~PAGE_EXEC
;
2354 if (attrs
& (1 << 5)) {
2355 /* Write access forbidden */
2356 if (access_type
== 1) {
2359 *prot
&= ~PAGE_WRITE
;
2362 *phys_ptr
= descaddr
;
2363 *page_size_ptr
= page_size
;
2367 /* Long-descriptor format IFSR/DFSR value */
2368 return (1 << 9) | (fault_type
<< 2) | level
;
2371 static int get_phys_addr_mpu(CPUARMState
*env
, uint32_t address
,
2372 int access_type
, int is_user
,
2373 hwaddr
*phys_ptr
, int *prot
)
2379 *phys_ptr
= address
;
2380 for (n
= 7; n
>= 0; n
--) {
2381 base
= env
->cp15
.c6_region
[n
];
2382 if ((base
& 1) == 0)
2384 mask
= 1 << ((base
>> 1) & 0x1f);
2385 /* Keep this shift separate from the above to avoid an
2386 (undefined) << 32. */
2387 mask
= (mask
<< 1) - 1;
2388 if (((base
^ address
) & ~mask
) == 0)
2394 if (access_type
== 2) {
2395 mask
= env
->cp15
.c5_insn
;
2397 mask
= env
->cp15
.c5_data
;
2399 mask
= (mask
>> (n
* 4)) & 0xf;
2406 *prot
= PAGE_READ
| PAGE_WRITE
;
2411 *prot
|= PAGE_WRITE
;
2414 *prot
= PAGE_READ
| PAGE_WRITE
;
2425 /* Bad permission. */
2432 /* get_phys_addr - get the physical address for this virtual address
2434 * Find the physical address corresponding to the given virtual address,
2435 * by doing a translation table walk on MMU based systems or using the
2436 * MPU state on MPU based systems.
2438 * Returns 0 if the translation was successful. Otherwise, phys_ptr,
2439 * prot and page_size are not filled in, and the return value provides
2440 * information on why the translation aborted, in the format of a
2441 * DFSR/IFSR fault register, with the following caveats:
2442 * * we honour the short vs long DFSR format differences.
2443 * * the WnR bit is never set (the caller must do this).
2444 * * for MPU based systems we don't bother to return a full FSR format
2448 * @address: virtual address to get physical address for
2449 * @access_type: 0 for read, 1 for write, 2 for execute
2450 * @is_user: 0 for privileged access, 1 for user
2451 * @phys_ptr: set to the physical address corresponding to the virtual address
2452 * @prot: set to the permissions for the page containing phys_ptr
2453 * @page_size: set to the size of the page containing phys_ptr
2455 static inline int get_phys_addr(CPUARMState
*env
, uint32_t address
,
2456 int access_type
, int is_user
,
2457 hwaddr
*phys_ptr
, int *prot
,
2458 target_ulong
*page_size
)
2460 /* Fast Context Switch Extension. */
2461 if (address
< 0x02000000)
2462 address
+= env
->cp15
.c13_fcse
;
2464 if ((env
->cp15
.c1_sys
& 1) == 0) {
2465 /* MMU/MPU disabled. */
2466 *phys_ptr
= address
;
2467 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
2468 *page_size
= TARGET_PAGE_SIZE
;
2470 } else if (arm_feature(env
, ARM_FEATURE_MPU
)) {
2471 *page_size
= TARGET_PAGE_SIZE
;
2472 return get_phys_addr_mpu(env
, address
, access_type
, is_user
, phys_ptr
,
2474 } else if (extended_addresses_enabled(env
)) {
2475 return get_phys_addr_lpae(env
, address
, access_type
, is_user
, phys_ptr
,
2477 } else if (env
->cp15
.c1_sys
& (1 << 23)) {
2478 return get_phys_addr_v6(env
, address
, access_type
, is_user
, phys_ptr
,
2481 return get_phys_addr_v5(env
, address
, access_type
, is_user
, phys_ptr
,
2486 int cpu_arm_handle_mmu_fault (CPUARMState
*env
, target_ulong address
,
2487 int access_type
, int mmu_idx
)
2490 target_ulong page_size
;
2494 is_user
= mmu_idx
== MMU_USER_IDX
;
2495 ret
= get_phys_addr(env
, address
, access_type
, is_user
, &phys_addr
, &prot
,
2498 /* Map a single [sub]page. */
2499 phys_addr
&= ~(hwaddr
)0x3ff;
2500 address
&= ~(uint32_t)0x3ff;
2501 tlb_set_page (env
, address
, phys_addr
, prot
, mmu_idx
, page_size
);
2505 if (access_type
== 2) {
2506 env
->cp15
.c5_insn
= ret
;
2507 env
->cp15
.c6_insn
= address
;
2508 env
->exception_index
= EXCP_PREFETCH_ABORT
;
2510 env
->cp15
.c5_data
= ret
;
2511 if (access_type
== 1 && arm_feature(env
, ARM_FEATURE_V6
))
2512 env
->cp15
.c5_data
|= (1 << 11);
2513 env
->cp15
.c6_data
= address
;
2514 env
->exception_index
= EXCP_DATA_ABORT
;
2519 hwaddr
cpu_get_phys_page_debug(CPUARMState
*env
, target_ulong addr
)
2522 target_ulong page_size
;
2526 ret
= get_phys_addr(env
, addr
, 0, 0, &phys_addr
, &prot
, &page_size
);
2534 void HELPER(set_r13_banked
)(CPUARMState
*env
, uint32_t mode
, uint32_t val
)
2536 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2537 env
->regs
[13] = val
;
2539 env
->banked_r13
[bank_number(env
, mode
)] = val
;
2543 uint32_t HELPER(get_r13_banked
)(CPUARMState
*env
, uint32_t mode
)
2545 if ((env
->uncached_cpsr
& CPSR_M
) == mode
) {
2546 return env
->regs
[13];
2548 return env
->banked_r13
[bank_number(env
, mode
)];
2552 uint32_t HELPER(v7m_mrs
)(CPUARMState
*env
, uint32_t reg
)
2556 return xpsr_read(env
) & 0xf8000000;
2558 return xpsr_read(env
) & 0xf80001ff;
2560 return xpsr_read(env
) & 0xff00fc00;
2562 return xpsr_read(env
) & 0xff00fdff;
2564 return xpsr_read(env
) & 0x000001ff;
2566 return xpsr_read(env
) & 0x0700fc00;
2568 return xpsr_read(env
) & 0x0700edff;
2570 return env
->v7m
.current_sp
? env
->v7m
.other_sp
: env
->regs
[13];
2572 return env
->v7m
.current_sp
? env
->regs
[13] : env
->v7m
.other_sp
;
2573 case 16: /* PRIMASK */
2574 return (env
->uncached_cpsr
& CPSR_I
) != 0;
2575 case 17: /* BASEPRI */
2576 case 18: /* BASEPRI_MAX */
2577 return env
->v7m
.basepri
;
2578 case 19: /* FAULTMASK */
2579 return (env
->uncached_cpsr
& CPSR_F
) != 0;
2580 case 20: /* CONTROL */
2581 return env
->v7m
.control
;
2583 /* ??? For debugging only. */
2584 cpu_abort(env
, "Unimplemented system register read (%d)\n", reg
);
2589 void HELPER(v7m_msr
)(CPUARMState
*env
, uint32_t reg
, uint32_t val
)
2593 xpsr_write(env
, val
, 0xf8000000);
2596 xpsr_write(env
, val
, 0xf8000000);
2599 xpsr_write(env
, val
, 0xfe00fc00);
2602 xpsr_write(env
, val
, 0xfe00fc00);
2605 /* IPSR bits are readonly. */
2608 xpsr_write(env
, val
, 0x0600fc00);
2611 xpsr_write(env
, val
, 0x0600fc00);
2614 if (env
->v7m
.current_sp
)
2615 env
->v7m
.other_sp
= val
;
2617 env
->regs
[13] = val
;
2620 if (env
->v7m
.current_sp
)
2621 env
->regs
[13] = val
;
2623 env
->v7m
.other_sp
= val
;
2625 case 16: /* PRIMASK */
2627 env
->uncached_cpsr
|= CPSR_I
;
2629 env
->uncached_cpsr
&= ~CPSR_I
;
2631 case 17: /* BASEPRI */
2632 env
->v7m
.basepri
= val
& 0xff;
2634 case 18: /* BASEPRI_MAX */
2636 if (val
!= 0 && (val
< env
->v7m
.basepri
|| env
->v7m
.basepri
== 0))
2637 env
->v7m
.basepri
= val
;
2639 case 19: /* FAULTMASK */
2641 env
->uncached_cpsr
|= CPSR_F
;
2643 env
->uncached_cpsr
&= ~CPSR_F
;
2645 case 20: /* CONTROL */
2646 env
->v7m
.control
= val
& 3;
2647 switch_v7m_sp(env
, (val
& 2) != 0);
2650 /* ??? For debugging only. */
2651 cpu_abort(env
, "Unimplemented system register write (%d)\n", reg
);
2658 /* Note that signed overflow is undefined in C. The following routines are
2659 careful to use unsigned types where modulo arithmetic is required.
2660 Failure to do so _will_ break on newer gcc. */
2662 /* Signed saturating arithmetic. */
2664 /* Perform 16-bit signed saturating addition. */
2665 static inline uint16_t add16_sat(uint16_t a
, uint16_t b
)
2670 if (((res
^ a
) & 0x8000) && !((a
^ b
) & 0x8000)) {
2679 /* Perform 8-bit signed saturating addition. */
2680 static inline uint8_t add8_sat(uint8_t a
, uint8_t b
)
2685 if (((res
^ a
) & 0x80) && !((a
^ b
) & 0x80)) {
2694 /* Perform 16-bit signed saturating subtraction. */
2695 static inline uint16_t sub16_sat(uint16_t a
, uint16_t b
)
2700 if (((res
^ a
) & 0x8000) && ((a
^ b
) & 0x8000)) {
2709 /* Perform 8-bit signed saturating subtraction. */
2710 static inline uint8_t sub8_sat(uint8_t a
, uint8_t b
)
2715 if (((res
^ a
) & 0x80) && ((a
^ b
) & 0x80)) {
2724 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2725 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2726 #define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2727 #define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2730 #include "op_addsub.h"
2732 /* Unsigned saturating arithmetic. */
2733 static inline uint16_t add16_usat(uint16_t a
, uint16_t b
)
2742 static inline uint16_t sub16_usat(uint16_t a
, uint16_t b
)
2750 static inline uint8_t add8_usat(uint8_t a
, uint8_t b
)
2759 static inline uint8_t sub8_usat(uint8_t a
, uint8_t b
)
2767 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2768 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2769 #define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2770 #define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2773 #include "op_addsub.h"
2775 /* Signed modulo arithmetic. */
2776 #define SARITH16(a, b, n, op) do { \
2778 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
2779 RESULT(sum, n, 16); \
2781 ge |= 3 << (n * 2); \
2784 #define SARITH8(a, b, n, op) do { \
2786 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
2787 RESULT(sum, n, 8); \
2793 #define ADD16(a, b, n) SARITH16(a, b, n, +)
2794 #define SUB16(a, b, n) SARITH16(a, b, n, -)
2795 #define ADD8(a, b, n) SARITH8(a, b, n, +)
2796 #define SUB8(a, b, n) SARITH8(a, b, n, -)
2800 #include "op_addsub.h"
2802 /* Unsigned modulo arithmetic. */
2803 #define ADD16(a, b, n) do { \
2805 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2806 RESULT(sum, n, 16); \
2807 if ((sum >> 16) == 1) \
2808 ge |= 3 << (n * 2); \
2811 #define ADD8(a, b, n) do { \
2813 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2814 RESULT(sum, n, 8); \
2815 if ((sum >> 8) == 1) \
2819 #define SUB16(a, b, n) do { \
2821 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2822 RESULT(sum, n, 16); \
2823 if ((sum >> 16) == 0) \
2824 ge |= 3 << (n * 2); \
2827 #define SUB8(a, b, n) do { \
2829 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2830 RESULT(sum, n, 8); \
2831 if ((sum >> 8) == 0) \
2838 #include "op_addsub.h"
2840 /* Halved signed arithmetic. */
2841 #define ADD16(a, b, n) \
2842 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2843 #define SUB16(a, b, n) \
2844 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2845 #define ADD8(a, b, n) \
2846 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2847 #define SUB8(a, b, n) \
2848 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2851 #include "op_addsub.h"
2853 /* Halved unsigned arithmetic. */
2854 #define ADD16(a, b, n) \
2855 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2856 #define SUB16(a, b, n) \
2857 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2858 #define ADD8(a, b, n) \
2859 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2860 #define SUB8(a, b, n) \
2861 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2864 #include "op_addsub.h"
2866 static inline uint8_t do_usad(uint8_t a
, uint8_t b
)
2874 /* Unsigned sum of absolute byte differences. */
2875 uint32_t HELPER(usad8
)(uint32_t a
, uint32_t b
)
2878 sum
= do_usad(a
, b
);
2879 sum
+= do_usad(a
>> 8, b
>> 8);
2880 sum
+= do_usad(a
>> 16, b
>>16);
2881 sum
+= do_usad(a
>> 24, b
>> 24);
2885 /* For ARMv6 SEL instruction. */
2886 uint32_t HELPER(sel_flags
)(uint32_t flags
, uint32_t a
, uint32_t b
)
2899 return (a
& mask
) | (b
& ~mask
);
2902 uint32_t HELPER(logicq_cc
)(uint64_t val
)
2904 return (val
>> 32) | (val
!= 0);
2907 /* VFP support. We follow the convention used for VFP instructions:
2908 Single precision routines have a "s" suffix, double precision a
2911 /* Convert host exception flags to vfp form. */
2912 static inline int vfp_exceptbits_from_host(int host_bits
)
2914 int target_bits
= 0;
2916 if (host_bits
& float_flag_invalid
)
2918 if (host_bits
& float_flag_divbyzero
)
2920 if (host_bits
& float_flag_overflow
)
2922 if (host_bits
& (float_flag_underflow
| float_flag_output_denormal
))
2924 if (host_bits
& float_flag_inexact
)
2925 target_bits
|= 0x10;
2926 if (host_bits
& float_flag_input_denormal
)
2927 target_bits
|= 0x80;
2931 uint32_t HELPER(vfp_get_fpscr
)(CPUARMState
*env
)
2936 fpscr
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & 0xffc8ffff)
2937 | (env
->vfp
.vec_len
<< 16)
2938 | (env
->vfp
.vec_stride
<< 20);
2939 i
= get_float_exception_flags(&env
->vfp
.fp_status
);
2940 i
|= get_float_exception_flags(&env
->vfp
.standard_fp_status
);
2941 fpscr
|= vfp_exceptbits_from_host(i
);
2945 uint32_t vfp_get_fpscr(CPUARMState
*env
)
2947 return HELPER(vfp_get_fpscr
)(env
);
2950 /* Convert vfp exception flags to target form. */
2951 static inline int vfp_exceptbits_to_host(int target_bits
)
2955 if (target_bits
& 1)
2956 host_bits
|= float_flag_invalid
;
2957 if (target_bits
& 2)
2958 host_bits
|= float_flag_divbyzero
;
2959 if (target_bits
& 4)
2960 host_bits
|= float_flag_overflow
;
2961 if (target_bits
& 8)
2962 host_bits
|= float_flag_underflow
;
2963 if (target_bits
& 0x10)
2964 host_bits
|= float_flag_inexact
;
2965 if (target_bits
& 0x80)
2966 host_bits
|= float_flag_input_denormal
;
2970 void HELPER(vfp_set_fpscr
)(CPUARMState
*env
, uint32_t val
)
2975 changed
= env
->vfp
.xregs
[ARM_VFP_FPSCR
];
2976 env
->vfp
.xregs
[ARM_VFP_FPSCR
] = (val
& 0xffc8ffff);
2977 env
->vfp
.vec_len
= (val
>> 16) & 7;
2978 env
->vfp
.vec_stride
= (val
>> 20) & 3;
2981 if (changed
& (3 << 22)) {
2982 i
= (val
>> 22) & 3;
2985 i
= float_round_nearest_even
;
2991 i
= float_round_down
;
2994 i
= float_round_to_zero
;
2997 set_float_rounding_mode(i
, &env
->vfp
.fp_status
);
2999 if (changed
& (1 << 24)) {
3000 set_flush_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
3001 set_flush_inputs_to_zero((val
& (1 << 24)) != 0, &env
->vfp
.fp_status
);
3003 if (changed
& (1 << 25))
3004 set_default_nan_mode((val
& (1 << 25)) != 0, &env
->vfp
.fp_status
);
3006 i
= vfp_exceptbits_to_host(val
);
3007 set_float_exception_flags(i
, &env
->vfp
.fp_status
);
3008 set_float_exception_flags(0, &env
->vfp
.standard_fp_status
);
3011 void vfp_set_fpscr(CPUARMState
*env
, uint32_t val
)
3013 HELPER(vfp_set_fpscr
)(env
, val
);
3016 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
3018 #define VFP_BINOP(name) \
3019 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
3021 float_status *fpst = fpstp; \
3022 return float32_ ## name(a, b, fpst); \
3024 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
3026 float_status *fpst = fpstp; \
3027 return float64_ ## name(a, b, fpst); \
3035 float32
VFP_HELPER(neg
, s
)(float32 a
)
3037 return float32_chs(a
);
3040 float64
VFP_HELPER(neg
, d
)(float64 a
)
3042 return float64_chs(a
);
3045 float32
VFP_HELPER(abs
, s
)(float32 a
)
3047 return float32_abs(a
);
3050 float64
VFP_HELPER(abs
, d
)(float64 a
)
3052 return float64_abs(a
);
3055 float32
VFP_HELPER(sqrt
, s
)(float32 a
, CPUARMState
*env
)
3057 return float32_sqrt(a
, &env
->vfp
.fp_status
);
3060 float64
VFP_HELPER(sqrt
, d
)(float64 a
, CPUARMState
*env
)
3062 return float64_sqrt(a
, &env
->vfp
.fp_status
);
3065 /* XXX: check quiet/signaling case */
3066 #define DO_VFP_cmp(p, type) \
3067 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
3070 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
3071 case 0: flags = 0x6; break; \
3072 case -1: flags = 0x8; break; \
3073 case 1: flags = 0x2; break; \
3074 default: case 2: flags = 0x3; break; \
3076 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3077 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3079 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
3082 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
3083 case 0: flags = 0x6; break; \
3084 case -1: flags = 0x8; break; \
3085 case 1: flags = 0x2; break; \
3086 default: case 2: flags = 0x3; break; \
3088 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
3089 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
3091 DO_VFP_cmp(s
, float32
)
3092 DO_VFP_cmp(d
, float64
)
3095 /* Integer to float and float to integer conversions */
3097 #define CONV_ITOF(name, fsz, sign) \
3098 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
3100 float_status *fpst = fpstp; \
3101 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
3104 #define CONV_FTOI(name, fsz, sign, round) \
3105 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
3107 float_status *fpst = fpstp; \
3108 if (float##fsz##_is_any_nan(x)) { \
3109 float_raise(float_flag_invalid, fpst); \
3112 return float##fsz##_to_##sign##int32##round(x, fpst); \
3115 #define FLOAT_CONVS(name, p, fsz, sign) \
3116 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
3117 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
3118 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
3120 FLOAT_CONVS(si
, s
, 32, )
3121 FLOAT_CONVS(si
, d
, 64, )
3122 FLOAT_CONVS(ui
, s
, 32, u
)
3123 FLOAT_CONVS(ui
, d
, 64, u
)
3129 /* floating point conversion */
3130 float64
VFP_HELPER(fcvtd
, s
)(float32 x
, CPUARMState
*env
)
3132 float64 r
= float32_to_float64(x
, &env
->vfp
.fp_status
);
3133 /* ARM requires that S<->D conversion of any kind of NaN generates
3134 * a quiet NaN by forcing the most significant frac bit to 1.
3136 return float64_maybe_silence_nan(r
);
3139 float32
VFP_HELPER(fcvts
, d
)(float64 x
, CPUARMState
*env
)
3141 float32 r
= float64_to_float32(x
, &env
->vfp
.fp_status
);
3142 /* ARM requires that S<->D conversion of any kind of NaN generates
3143 * a quiet NaN by forcing the most significant frac bit to 1.
3145 return float32_maybe_silence_nan(r
);
3148 /* VFP3 fixed point conversion. */
3149 #define VFP_CONV_FIX(name, p, fsz, itype, sign) \
3150 float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
3153 float_status *fpst = fpstp; \
3155 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
3156 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
3158 uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
3161 float_status *fpst = fpstp; \
3163 if (float##fsz##_is_any_nan(x)) { \
3164 float_raise(float_flag_invalid, fpst); \
3167 tmp = float##fsz##_scalbn(x, shift, fpst); \
3168 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
3171 VFP_CONV_FIX(sh
, d
, 64, int16
, )
3172 VFP_CONV_FIX(sl
, d
, 64, int32
, )
3173 VFP_CONV_FIX(uh
, d
, 64, uint16
, u
)
3174 VFP_CONV_FIX(ul
, d
, 64, uint32
, u
)
3175 VFP_CONV_FIX(sh
, s
, 32, int16
, )
3176 VFP_CONV_FIX(sl
, s
, 32, int32
, )
3177 VFP_CONV_FIX(uh
, s
, 32, uint16
, u
)
3178 VFP_CONV_FIX(ul
, s
, 32, uint32
, u
)
3181 /* Half precision conversions. */
3182 static float32
do_fcvt_f16_to_f32(uint32_t a
, CPUARMState
*env
, float_status
*s
)
3184 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
3185 float32 r
= float16_to_float32(make_float16(a
), ieee
, s
);
3187 return float32_maybe_silence_nan(r
);
3192 static uint32_t do_fcvt_f32_to_f16(float32 a
, CPUARMState
*env
, float_status
*s
)
3194 int ieee
= (env
->vfp
.xregs
[ARM_VFP_FPSCR
] & (1 << 26)) == 0;
3195 float16 r
= float32_to_float16(a
, ieee
, s
);
3197 r
= float16_maybe_silence_nan(r
);
3199 return float16_val(r
);
3202 float32
HELPER(neon_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
3204 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.standard_fp_status
);
3207 uint32_t HELPER(neon_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
3209 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.standard_fp_status
);
3212 float32
HELPER(vfp_fcvt_f16_to_f32
)(uint32_t a
, CPUARMState
*env
)
3214 return do_fcvt_f16_to_f32(a
, env
, &env
->vfp
.fp_status
);
3217 uint32_t HELPER(vfp_fcvt_f32_to_f16
)(float32 a
, CPUARMState
*env
)
3219 return do_fcvt_f32_to_f16(a
, env
, &env
->vfp
.fp_status
);
3222 #define float32_two make_float32(0x40000000)
3223 #define float32_three make_float32(0x40400000)
3224 #define float32_one_point_five make_float32(0x3fc00000)
3226 float32
HELPER(recps_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
3228 float_status
*s
= &env
->vfp
.standard_fp_status
;
3229 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
3230 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
3231 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
3232 float_raise(float_flag_input_denormal
, s
);
3236 return float32_sub(float32_two
, float32_mul(a
, b
, s
), s
);
3239 float32
HELPER(rsqrts_f32
)(float32 a
, float32 b
, CPUARMState
*env
)
3241 float_status
*s
= &env
->vfp
.standard_fp_status
;
3243 if ((float32_is_infinity(a
) && float32_is_zero_or_denormal(b
)) ||
3244 (float32_is_infinity(b
) && float32_is_zero_or_denormal(a
))) {
3245 if (!(float32_is_zero(a
) || float32_is_zero(b
))) {
3246 float_raise(float_flag_input_denormal
, s
);
3248 return float32_one_point_five
;
3250 product
= float32_mul(a
, b
, s
);
3251 return float32_div(float32_sub(float32_three
, product
, s
), float32_two
, s
);
3256 /* Constants 256 and 512 are used in some helpers; we avoid relying on
3257 * int->float conversions at run-time. */
3258 #define float64_256 make_float64(0x4070000000000000LL)
3259 #define float64_512 make_float64(0x4080000000000000LL)
3261 /* The algorithm that must be used to calculate the estimate
3262 * is specified by the ARM ARM.
3264 static float64
recip_estimate(float64 a
, CPUARMState
*env
)
3266 /* These calculations mustn't set any fp exception flags,
3267 * so we use a local copy of the fp_status.
3269 float_status dummy_status
= env
->vfp
.standard_fp_status
;
3270 float_status
*s
= &dummy_status
;
3271 /* q = (int)(a * 512.0) */
3272 float64 q
= float64_mul(float64_512
, a
, s
);
3273 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
3275 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
3276 q
= int64_to_float64(q_int
, s
);
3277 q
= float64_add(q
, float64_half
, s
);
3278 q
= float64_div(q
, float64_512
, s
);
3279 q
= float64_div(float64_one
, q
, s
);
3281 /* s = (int)(256.0 * r + 0.5) */
3282 q
= float64_mul(q
, float64_256
, s
);
3283 q
= float64_add(q
, float64_half
, s
);
3284 q_int
= float64_to_int64_round_to_zero(q
, s
);
3286 /* return (double)s / 256.0 */
3287 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
3290 float32
HELPER(recpe_f32
)(float32 a
, CPUARMState
*env
)
3292 float_status
*s
= &env
->vfp
.standard_fp_status
;
3294 uint32_t val32
= float32_val(a
);
3297 int a_exp
= (val32
& 0x7f800000) >> 23;
3298 int sign
= val32
& 0x80000000;
3300 if (float32_is_any_nan(a
)) {
3301 if (float32_is_signaling_nan(a
)) {
3302 float_raise(float_flag_invalid
, s
);
3304 return float32_default_nan
;
3305 } else if (float32_is_infinity(a
)) {
3306 return float32_set_sign(float32_zero
, float32_is_neg(a
));
3307 } else if (float32_is_zero_or_denormal(a
)) {
3308 if (!float32_is_zero(a
)) {
3309 float_raise(float_flag_input_denormal
, s
);
3311 float_raise(float_flag_divbyzero
, s
);
3312 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
3313 } else if (a_exp
>= 253) {
3314 float_raise(float_flag_underflow
, s
);
3315 return float32_set_sign(float32_zero
, float32_is_neg(a
));
3318 f64
= make_float64((0x3feULL
<< 52)
3319 | ((int64_t)(val32
& 0x7fffff) << 29));
3321 result_exp
= 253 - a_exp
;
3323 f64
= recip_estimate(f64
, env
);
3326 | ((result_exp
& 0xff) << 23)
3327 | ((float64_val(f64
) >> 29) & 0x7fffff);
3328 return make_float32(val32
);
3331 /* The algorithm that must be used to calculate the estimate
3332 * is specified by the ARM ARM.
3334 static float64
recip_sqrt_estimate(float64 a
, CPUARMState
*env
)
3336 /* These calculations mustn't set any fp exception flags,
3337 * so we use a local copy of the fp_status.
3339 float_status dummy_status
= env
->vfp
.standard_fp_status
;
3340 float_status
*s
= &dummy_status
;
3344 if (float64_lt(a
, float64_half
, s
)) {
3345 /* range 0.25 <= a < 0.5 */
3347 /* a in units of 1/512 rounded down */
3348 /* q0 = (int)(a * 512.0); */
3349 q
= float64_mul(float64_512
, a
, s
);
3350 q_int
= float64_to_int64_round_to_zero(q
, s
);
3352 /* reciprocal root r */
3353 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
3354 q
= int64_to_float64(q_int
, s
);
3355 q
= float64_add(q
, float64_half
, s
);
3356 q
= float64_div(q
, float64_512
, s
);
3357 q
= float64_sqrt(q
, s
);
3358 q
= float64_div(float64_one
, q
, s
);
3360 /* range 0.5 <= a < 1.0 */
3362 /* a in units of 1/256 rounded down */
3363 /* q1 = (int)(a * 256.0); */
3364 q
= float64_mul(float64_256
, a
, s
);
3365 int64_t q_int
= float64_to_int64_round_to_zero(q
, s
);
3367 /* reciprocal root r */
3368 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3369 q
= int64_to_float64(q_int
, s
);
3370 q
= float64_add(q
, float64_half
, s
);
3371 q
= float64_div(q
, float64_256
, s
);
3372 q
= float64_sqrt(q
, s
);
3373 q
= float64_div(float64_one
, q
, s
);
3375 /* r in units of 1/256 rounded to nearest */
3376 /* s = (int)(256.0 * r + 0.5); */
3378 q
= float64_mul(q
, float64_256
,s
);
3379 q
= float64_add(q
, float64_half
, s
);
3380 q_int
= float64_to_int64_round_to_zero(q
, s
);
3382 /* return (double)s / 256.0;*/
3383 return float64_div(int64_to_float64(q_int
, s
), float64_256
, s
);
3386 float32
HELPER(rsqrte_f32
)(float32 a
, CPUARMState
*env
)
3388 float_status
*s
= &env
->vfp
.standard_fp_status
;
3394 val
= float32_val(a
);
3396 if (float32_is_any_nan(a
)) {
3397 if (float32_is_signaling_nan(a
)) {
3398 float_raise(float_flag_invalid
, s
);
3400 return float32_default_nan
;
3401 } else if (float32_is_zero_or_denormal(a
)) {
3402 if (!float32_is_zero(a
)) {
3403 float_raise(float_flag_input_denormal
, s
);
3405 float_raise(float_flag_divbyzero
, s
);
3406 return float32_set_sign(float32_infinity
, float32_is_neg(a
));
3407 } else if (float32_is_neg(a
)) {
3408 float_raise(float_flag_invalid
, s
);
3409 return float32_default_nan
;
3410 } else if (float32_is_infinity(a
)) {
3411 return float32_zero
;
3414 /* Normalize to a double-precision value between 0.25 and 1.0,
3415 * preserving the parity of the exponent. */
3416 if ((val
& 0x800000) == 0) {
3417 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3419 | ((uint64_t)(val
& 0x7fffff) << 29));
3421 f64
= make_float64(((uint64_t)(val
& 0x80000000) << 32)
3423 | ((uint64_t)(val
& 0x7fffff) << 29));
3426 result_exp
= (380 - ((val
& 0x7f800000) >> 23)) / 2;
3428 f64
= recip_sqrt_estimate(f64
, env
);
3430 val64
= float64_val(f64
);
3432 val
= ((result_exp
& 0xff) << 23)
3433 | ((val64
>> 29) & 0x7fffff);
3434 return make_float32(val
);
3437 uint32_t HELPER(recpe_u32
)(uint32_t a
, CPUARMState
*env
)
3441 if ((a
& 0x80000000) == 0) {
3445 f64
= make_float64((0x3feULL
<< 52)
3446 | ((int64_t)(a
& 0x7fffffff) << 21));
3448 f64
= recip_estimate (f64
, env
);
3450 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3453 uint32_t HELPER(rsqrte_u32
)(uint32_t a
, CPUARMState
*env
)
3457 if ((a
& 0xc0000000) == 0) {
3461 if (a
& 0x80000000) {
3462 f64
= make_float64((0x3feULL
<< 52)
3463 | ((uint64_t)(a
& 0x7fffffff) << 21));
3464 } else { /* bits 31-30 == '01' */
3465 f64
= make_float64((0x3fdULL
<< 52)
3466 | ((uint64_t)(a
& 0x3fffffff) << 22));
3469 f64
= recip_sqrt_estimate(f64
, env
);
3471 return 0x80000000 | ((float64_val(f64
) >> 21) & 0x7fffffff);
3474 /* VFPv4 fused multiply-accumulate */
3475 float32
VFP_HELPER(muladd
, s
)(float32 a
, float32 b
, float32 c
, void *fpstp
)
3477 float_status
*fpst
= fpstp
;
3478 return float32_muladd(a
, b
, c
, 0, fpst
);
3481 float64
VFP_HELPER(muladd
, d
)(float64 a
, float64 b
, float64 c
, void *fpstp
)
3483 float_status
*fpst
= fpstp
;
3484 return float64_muladd(a
, b
, c
, 0, fpst
);