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kvm: i386: fix LAPIC TSC deadline timer save/restore
[qemu.git] / target-i386 / kvm.c
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
17 #include <sys/mman.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
22
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm.h"
26 #include "kvm_i386.h"
27 #include "cpu.h"
28 #include "exec/gdbstub.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/config-file.h"
31 #include "hw/i386/pc.h"
32 #include "hw/i386/apic.h"
33 #include "exec/ioport.h"
34 #include "hyperv.h"
35 #include "hw/pci/pci.h"
36
37 //#define DEBUG_KVM
38
39 #ifdef DEBUG_KVM
40 #define DPRINTF(fmt, ...) \
41 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
42 #else
43 #define DPRINTF(fmt, ...) \
44 do { } while (0)
45 #endif
46
47 #define MSR_KVM_WALL_CLOCK 0x11
48 #define MSR_KVM_SYSTEM_TIME 0x12
49
50 #ifndef BUS_MCEERR_AR
51 #define BUS_MCEERR_AR 4
52 #endif
53 #ifndef BUS_MCEERR_AO
54 #define BUS_MCEERR_AO 5
55 #endif
56
57 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
58 KVM_CAP_INFO(SET_TSS_ADDR),
59 KVM_CAP_INFO(EXT_CPUID),
60 KVM_CAP_INFO(MP_STATE),
61 KVM_CAP_LAST_INFO
62 };
63
64 static bool has_msr_star;
65 static bool has_msr_hsave_pa;
66 static bool has_msr_tsc_adjust;
67 static bool has_msr_tsc_deadline;
68 static bool has_msr_feature_control;
69 static bool has_msr_async_pf_en;
70 static bool has_msr_pv_eoi_en;
71 static bool has_msr_misc_enable;
72 static bool has_msr_kvm_steal_time;
73 static int lm_capable_kernel;
74
75 static bool has_msr_architectural_pmu;
76 static uint32_t num_architectural_pmu_counters;
77
78 bool kvm_allows_irq0_override(void)
79 {
80 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
81 }
82
83 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
84 {
85 struct kvm_cpuid2 *cpuid;
86 int r, size;
87
88 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
89 cpuid = (struct kvm_cpuid2 *)g_malloc0(size);
90 cpuid->nent = max;
91 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
92 if (r == 0 && cpuid->nent >= max) {
93 r = -E2BIG;
94 }
95 if (r < 0) {
96 if (r == -E2BIG) {
97 g_free(cpuid);
98 return NULL;
99 } else {
100 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
101 strerror(-r));
102 exit(1);
103 }
104 }
105 return cpuid;
106 }
107
108 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
109 * for all entries.
110 */
111 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
112 {
113 struct kvm_cpuid2 *cpuid;
114 int max = 1;
115 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
116 max *= 2;
117 }
118 return cpuid;
119 }
120
121 struct kvm_para_features {
122 int cap;
123 int feature;
124 } para_features[] = {
125 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
126 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
127 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
128 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
129 { -1, -1 }
130 };
131
132 static int get_para_features(KVMState *s)
133 {
134 int i, features = 0;
135
136 for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
137 if (kvm_check_extension(s, para_features[i].cap)) {
138 features |= (1 << para_features[i].feature);
139 }
140 }
141
142 return features;
143 }
144
145
146 /* Returns the value for a specific register on the cpuid entry
147 */
148 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
149 {
150 uint32_t ret = 0;
151 switch (reg) {
152 case R_EAX:
153 ret = entry->eax;
154 break;
155 case R_EBX:
156 ret = entry->ebx;
157 break;
158 case R_ECX:
159 ret = entry->ecx;
160 break;
161 case R_EDX:
162 ret = entry->edx;
163 break;
164 }
165 return ret;
166 }
167
168 /* Find matching entry for function/index on kvm_cpuid2 struct
169 */
170 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
171 uint32_t function,
172 uint32_t index)
173 {
174 int i;
175 for (i = 0; i < cpuid->nent; ++i) {
176 if (cpuid->entries[i].function == function &&
177 cpuid->entries[i].index == index) {
178 return &cpuid->entries[i];
179 }
180 }
181 /* not found: */
182 return NULL;
183 }
184
185 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
186 uint32_t index, int reg)
187 {
188 struct kvm_cpuid2 *cpuid;
189 uint32_t ret = 0;
190 uint32_t cpuid_1_edx;
191 bool found = false;
192
193 cpuid = get_supported_cpuid(s);
194
195 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
196 if (entry) {
197 found = true;
198 ret = cpuid_entry_get_reg(entry, reg);
199 }
200
201 /* Fixups for the data returned by KVM, below */
202
203 if (function == 1 && reg == R_EDX) {
204 /* KVM before 2.6.30 misreports the following features */
205 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
206 } else if (function == 1 && reg == R_ECX) {
207 /* We can set the hypervisor flag, even if KVM does not return it on
208 * GET_SUPPORTED_CPUID
209 */
210 ret |= CPUID_EXT_HYPERVISOR;
211 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
212 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
213 * and the irqchip is in the kernel.
214 */
215 if (kvm_irqchip_in_kernel() &&
216 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
217 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
218 }
219
220 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
221 * without the in-kernel irqchip
222 */
223 if (!kvm_irqchip_in_kernel()) {
224 ret &= ~CPUID_EXT_X2APIC;
225 }
226 } else if (function == 0x80000001 && reg == R_EDX) {
227 /* On Intel, kvm returns cpuid according to the Intel spec,
228 * so add missing bits according to the AMD spec:
229 */
230 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
231 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
232 }
233
234 g_free(cpuid);
235
236 /* fallback for older kernels */
237 if ((function == KVM_CPUID_FEATURES) && !found) {
238 ret = get_para_features(s);
239 }
240
241 return ret;
242 }
243
244 typedef struct HWPoisonPage {
245 ram_addr_t ram_addr;
246 QLIST_ENTRY(HWPoisonPage) list;
247 } HWPoisonPage;
248
249 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
250 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
251
252 static void kvm_unpoison_all(void *param)
253 {
254 HWPoisonPage *page, *next_page;
255
256 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
257 QLIST_REMOVE(page, list);
258 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
259 g_free(page);
260 }
261 }
262
263 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
264 {
265 HWPoisonPage *page;
266
267 QLIST_FOREACH(page, &hwpoison_page_list, list) {
268 if (page->ram_addr == ram_addr) {
269 return;
270 }
271 }
272 page = g_malloc(sizeof(HWPoisonPage));
273 page->ram_addr = ram_addr;
274 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
275 }
276
277 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
278 int *max_banks)
279 {
280 int r;
281
282 r = kvm_check_extension(s, KVM_CAP_MCE);
283 if (r > 0) {
284 *max_banks = r;
285 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
286 }
287 return -ENOSYS;
288 }
289
290 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
291 {
292 CPUX86State *env = &cpu->env;
293 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
294 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
295 uint64_t mcg_status = MCG_STATUS_MCIP;
296
297 if (code == BUS_MCEERR_AR) {
298 status |= MCI_STATUS_AR | 0x134;
299 mcg_status |= MCG_STATUS_EIPV;
300 } else {
301 status |= 0xc0;
302 mcg_status |= MCG_STATUS_RIPV;
303 }
304 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
305 (MCM_ADDR_PHYS << 6) | 0xc,
306 cpu_x86_support_mca_broadcast(env) ?
307 MCE_INJECT_BROADCAST : 0);
308 }
309
310 static void hardware_memory_error(void)
311 {
312 fprintf(stderr, "Hardware memory error!\n");
313 exit(1);
314 }
315
316 int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
317 {
318 X86CPU *cpu = X86_CPU(c);
319 CPUX86State *env = &cpu->env;
320 ram_addr_t ram_addr;
321 hwaddr paddr;
322
323 if ((env->mcg_cap & MCG_SER_P) && addr
324 && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {
325 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
326 !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
327 fprintf(stderr, "Hardware memory error for memory used by "
328 "QEMU itself instead of guest system!\n");
329 /* Hope we are lucky for AO MCE */
330 if (code == BUS_MCEERR_AO) {
331 return 0;
332 } else {
333 hardware_memory_error();
334 }
335 }
336 kvm_hwpoison_page_add(ram_addr);
337 kvm_mce_inject(cpu, paddr, code);
338 } else {
339 if (code == BUS_MCEERR_AO) {
340 return 0;
341 } else if (code == BUS_MCEERR_AR) {
342 hardware_memory_error();
343 } else {
344 return 1;
345 }
346 }
347 return 0;
348 }
349
350 int kvm_arch_on_sigbus(int code, void *addr)
351 {
352 X86CPU *cpu = X86_CPU(first_cpu);
353
354 if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {
355 ram_addr_t ram_addr;
356 hwaddr paddr;
357
358 /* Hope we are lucky for AO MCE */
359 if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||
360 !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,
361 addr, &paddr)) {
362 fprintf(stderr, "Hardware memory error for memory used by "
363 "QEMU itself instead of guest system!: %p\n", addr);
364 return 0;
365 }
366 kvm_hwpoison_page_add(ram_addr);
367 kvm_mce_inject(X86_CPU(first_cpu), paddr, code);
368 } else {
369 if (code == BUS_MCEERR_AO) {
370 return 0;
371 } else if (code == BUS_MCEERR_AR) {
372 hardware_memory_error();
373 } else {
374 return 1;
375 }
376 }
377 return 0;
378 }
379
380 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
381 {
382 CPUX86State *env = &cpu->env;
383
384 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
385 unsigned int bank, bank_num = env->mcg_cap & 0xff;
386 struct kvm_x86_mce mce;
387
388 env->exception_injected = -1;
389
390 /*
391 * There must be at least one bank in use if an MCE is pending.
392 * Find it and use its values for the event injection.
393 */
394 for (bank = 0; bank < bank_num; bank++) {
395 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
396 break;
397 }
398 }
399 assert(bank < bank_num);
400
401 mce.bank = bank;
402 mce.status = env->mce_banks[bank * 4 + 1];
403 mce.mcg_status = env->mcg_status;
404 mce.addr = env->mce_banks[bank * 4 + 2];
405 mce.misc = env->mce_banks[bank * 4 + 3];
406
407 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
408 }
409 return 0;
410 }
411
412 static void cpu_update_state(void *opaque, int running, RunState state)
413 {
414 CPUX86State *env = opaque;
415
416 if (running) {
417 env->tsc_valid = false;
418 }
419 }
420
421 unsigned long kvm_arch_vcpu_id(CPUState *cs)
422 {
423 X86CPU *cpu = X86_CPU(cs);
424 return cpu->env.cpuid_apic_id;
425 }
426
427 #define KVM_MAX_CPUID_ENTRIES 100
428
429 int kvm_arch_init_vcpu(CPUState *cs)
430 {
431 struct {
432 struct kvm_cpuid2 cpuid;
433 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
434 } QEMU_PACKED cpuid_data;
435 X86CPU *cpu = X86_CPU(cs);
436 CPUX86State *env = &cpu->env;
437 uint32_t limit, i, j, cpuid_i;
438 uint32_t unused;
439 struct kvm_cpuid_entry2 *c;
440 uint32_t signature[3];
441 int r;
442
443 cpuid_i = 0;
444
445 /* Paravirtualization CPUIDs */
446 c = &cpuid_data.entries[cpuid_i++];
447 memset(c, 0, sizeof(*c));
448 c->function = KVM_CPUID_SIGNATURE;
449 if (!hyperv_enabled()) {
450 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
451 c->eax = 0;
452 } else {
453 memcpy(signature, "Microsoft Hv", 12);
454 c->eax = HYPERV_CPUID_MIN;
455 }
456 c->ebx = signature[0];
457 c->ecx = signature[1];
458 c->edx = signature[2];
459
460 c = &cpuid_data.entries[cpuid_i++];
461 memset(c, 0, sizeof(*c));
462 c->function = KVM_CPUID_FEATURES;
463 c->eax = env->features[FEAT_KVM];
464
465 if (hyperv_enabled()) {
466 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
467 c->eax = signature[0];
468
469 c = &cpuid_data.entries[cpuid_i++];
470 memset(c, 0, sizeof(*c));
471 c->function = HYPERV_CPUID_VERSION;
472 c->eax = 0x00001bbc;
473 c->ebx = 0x00060001;
474
475 c = &cpuid_data.entries[cpuid_i++];
476 memset(c, 0, sizeof(*c));
477 c->function = HYPERV_CPUID_FEATURES;
478 if (hyperv_relaxed_timing_enabled()) {
479 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
480 }
481 if (hyperv_vapic_recommended()) {
482 c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;
483 c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;
484 }
485
486 c = &cpuid_data.entries[cpuid_i++];
487 memset(c, 0, sizeof(*c));
488 c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;
489 if (hyperv_relaxed_timing_enabled()) {
490 c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;
491 }
492 if (hyperv_vapic_recommended()) {
493 c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;
494 }
495 c->ebx = hyperv_get_spinlock_retries();
496
497 c = &cpuid_data.entries[cpuid_i++];
498 memset(c, 0, sizeof(*c));
499 c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;
500 c->eax = 0x40;
501 c->ebx = 0x40;
502
503 c = &cpuid_data.entries[cpuid_i++];
504 memset(c, 0, sizeof(*c));
505 c->function = KVM_CPUID_SIGNATURE_NEXT;
506 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
507 c->eax = 0;
508 c->ebx = signature[0];
509 c->ecx = signature[1];
510 c->edx = signature[2];
511 }
512
513 has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);
514
515 has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);
516
517 has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);
518
519 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
520
521 for (i = 0; i <= limit; i++) {
522 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
523 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
524 abort();
525 }
526 c = &cpuid_data.entries[cpuid_i++];
527
528 switch (i) {
529 case 2: {
530 /* Keep reading function 2 till all the input is received */
531 int times;
532
533 c->function = i;
534 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
535 KVM_CPUID_FLAG_STATE_READ_NEXT;
536 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
537 times = c->eax & 0xff;
538
539 for (j = 1; j < times; ++j) {
540 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
541 fprintf(stderr, "cpuid_data is full, no space for "
542 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
543 abort();
544 }
545 c = &cpuid_data.entries[cpuid_i++];
546 c->function = i;
547 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
548 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
549 }
550 break;
551 }
552 case 4:
553 case 0xb:
554 case 0xd:
555 for (j = 0; ; j++) {
556 if (i == 0xd && j == 64) {
557 break;
558 }
559 c->function = i;
560 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
561 c->index = j;
562 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
563
564 if (i == 4 && c->eax == 0) {
565 break;
566 }
567 if (i == 0xb && !(c->ecx & 0xff00)) {
568 break;
569 }
570 if (i == 0xd && c->eax == 0) {
571 continue;
572 }
573 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
574 fprintf(stderr, "cpuid_data is full, no space for "
575 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
576 abort();
577 }
578 c = &cpuid_data.entries[cpuid_i++];
579 }
580 break;
581 default:
582 c->function = i;
583 c->flags = 0;
584 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
585 break;
586 }
587 }
588
589 if (limit >= 0x0a) {
590 uint32_t ver;
591
592 cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);
593 if ((ver & 0xff) > 0) {
594 has_msr_architectural_pmu = true;
595 num_architectural_pmu_counters = (ver & 0xff00) >> 8;
596
597 /* Shouldn't be more than 32, since that's the number of bits
598 * available in EBX to tell us _which_ counters are available.
599 * Play it safe.
600 */
601 if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {
602 num_architectural_pmu_counters = MAX_GP_COUNTERS;
603 }
604 }
605 }
606
607 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
608
609 for (i = 0x80000000; i <= limit; i++) {
610 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
611 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
612 abort();
613 }
614 c = &cpuid_data.entries[cpuid_i++];
615
616 c->function = i;
617 c->flags = 0;
618 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
619 }
620
621 /* Call Centaur's CPUID instructions they are supported. */
622 if (env->cpuid_xlevel2 > 0) {
623 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
624
625 for (i = 0xC0000000; i <= limit; i++) {
626 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
627 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
628 abort();
629 }
630 c = &cpuid_data.entries[cpuid_i++];
631
632 c->function = i;
633 c->flags = 0;
634 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
635 }
636 }
637
638 cpuid_data.cpuid.nent = cpuid_i;
639
640 if (((env->cpuid_version >> 8)&0xF) >= 6
641 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
642 (CPUID_MCE | CPUID_MCA)
643 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
644 uint64_t mcg_cap;
645 int banks;
646 int ret;
647
648 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
649 if (ret < 0) {
650 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
651 return ret;
652 }
653
654 if (banks > MCE_BANKS_DEF) {
655 banks = MCE_BANKS_DEF;
656 }
657 mcg_cap &= MCE_CAP_DEF;
658 mcg_cap |= banks;
659 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);
660 if (ret < 0) {
661 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
662 return ret;
663 }
664
665 env->mcg_cap = mcg_cap;
666 }
667
668 qemu_add_vm_change_state_handler(cpu_update_state, env);
669
670 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
671 if (c) {
672 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
673 !!(c->ecx & CPUID_EXT_SMX);
674 }
675
676 cpuid_data.cpuid.padding = 0;
677 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
678 if (r) {
679 return r;
680 }
681
682 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);
683 if (r && env->tsc_khz) {
684 r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);
685 if (r < 0) {
686 fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");
687 return r;
688 }
689 }
690
691 if (kvm_has_xsave()) {
692 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
693 }
694
695 return 0;
696 }
697
698 void kvm_arch_reset_vcpu(CPUState *cs)
699 {
700 X86CPU *cpu = X86_CPU(cs);
701 CPUX86State *env = &cpu->env;
702
703 env->exception_injected = -1;
704 env->interrupt_injected = -1;
705 env->xcr0 = 1;
706 if (kvm_irqchip_in_kernel()) {
707 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
708 KVM_MP_STATE_UNINITIALIZED;
709 } else {
710 env->mp_state = KVM_MP_STATE_RUNNABLE;
711 }
712 }
713
714 static int kvm_get_supported_msrs(KVMState *s)
715 {
716 static int kvm_supported_msrs;
717 int ret = 0;
718
719 /* first time */
720 if (kvm_supported_msrs == 0) {
721 struct kvm_msr_list msr_list, *kvm_msr_list;
722
723 kvm_supported_msrs = -1;
724
725 /* Obtain MSR list from KVM. These are the MSRs that we must
726 * save/restore */
727 msr_list.nmsrs = 0;
728 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
729 if (ret < 0 && ret != -E2BIG) {
730 return ret;
731 }
732 /* Old kernel modules had a bug and could write beyond the provided
733 memory. Allocate at least a safe amount of 1K. */
734 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
735 msr_list.nmsrs *
736 sizeof(msr_list.indices[0])));
737
738 kvm_msr_list->nmsrs = msr_list.nmsrs;
739 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
740 if (ret >= 0) {
741 int i;
742
743 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
744 if (kvm_msr_list->indices[i] == MSR_STAR) {
745 has_msr_star = true;
746 continue;
747 }
748 if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {
749 has_msr_hsave_pa = true;
750 continue;
751 }
752 if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {
753 has_msr_tsc_adjust = true;
754 continue;
755 }
756 if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
757 has_msr_tsc_deadline = true;
758 continue;
759 }
760 if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {
761 has_msr_misc_enable = true;
762 continue;
763 }
764 }
765 }
766
767 g_free(kvm_msr_list);
768 }
769
770 return ret;
771 }
772
773 int kvm_arch_init(KVMState *s)
774 {
775 uint64_t identity_base = 0xfffbc000;
776 uint64_t shadow_mem;
777 int ret;
778 struct utsname utsname;
779
780 ret = kvm_get_supported_msrs(s);
781 if (ret < 0) {
782 return ret;
783 }
784
785 uname(&utsname);
786 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
787
788 /*
789 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
790 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
791 * Since these must be part of guest physical memory, we need to allocate
792 * them, both by setting their start addresses in the kernel and by
793 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
794 *
795 * Older KVM versions may not support setting the identity map base. In
796 * that case we need to stick with the default, i.e. a 256K maximum BIOS
797 * size.
798 */
799 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
800 /* Allows up to 16M BIOSes. */
801 identity_base = 0xfeffc000;
802
803 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
804 if (ret < 0) {
805 return ret;
806 }
807 }
808
809 /* Set TSS base one page after EPT identity map. */
810 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
811 if (ret < 0) {
812 return ret;
813 }
814
815 /* Tell fw_cfg to notify the BIOS to reserve the range. */
816 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
817 if (ret < 0) {
818 fprintf(stderr, "e820_add_entry() table is full\n");
819 return ret;
820 }
821 qemu_register_reset(kvm_unpoison_all, NULL);
822
823 shadow_mem = qemu_opt_get_size(qemu_get_machine_opts(),
824 "kvm_shadow_mem", -1);
825 if (shadow_mem != -1) {
826 shadow_mem /= 4096;
827 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
828 if (ret < 0) {
829 return ret;
830 }
831 }
832 return 0;
833 }
834
835 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
836 {
837 lhs->selector = rhs->selector;
838 lhs->base = rhs->base;
839 lhs->limit = rhs->limit;
840 lhs->type = 3;
841 lhs->present = 1;
842 lhs->dpl = 3;
843 lhs->db = 0;
844 lhs->s = 1;
845 lhs->l = 0;
846 lhs->g = 0;
847 lhs->avl = 0;
848 lhs->unusable = 0;
849 }
850
851 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
852 {
853 unsigned flags = rhs->flags;
854 lhs->selector = rhs->selector;
855 lhs->base = rhs->base;
856 lhs->limit = rhs->limit;
857 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
858 lhs->present = (flags & DESC_P_MASK) != 0;
859 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
860 lhs->db = (flags >> DESC_B_SHIFT) & 1;
861 lhs->s = (flags & DESC_S_MASK) != 0;
862 lhs->l = (flags >> DESC_L_SHIFT) & 1;
863 lhs->g = (flags & DESC_G_MASK) != 0;
864 lhs->avl = (flags & DESC_AVL_MASK) != 0;
865 lhs->unusable = 0;
866 lhs->padding = 0;
867 }
868
869 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
870 {
871 lhs->selector = rhs->selector;
872 lhs->base = rhs->base;
873 lhs->limit = rhs->limit;
874 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
875 (rhs->present * DESC_P_MASK) |
876 (rhs->dpl << DESC_DPL_SHIFT) |
877 (rhs->db << DESC_B_SHIFT) |
878 (rhs->s * DESC_S_MASK) |
879 (rhs->l << DESC_L_SHIFT) |
880 (rhs->g * DESC_G_MASK) |
881 (rhs->avl * DESC_AVL_MASK);
882 }
883
884 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
885 {
886 if (set) {
887 *kvm_reg = *qemu_reg;
888 } else {
889 *qemu_reg = *kvm_reg;
890 }
891 }
892
893 static int kvm_getput_regs(X86CPU *cpu, int set)
894 {
895 CPUX86State *env = &cpu->env;
896 struct kvm_regs regs;
897 int ret = 0;
898
899 if (!set) {
900 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
901 if (ret < 0) {
902 return ret;
903 }
904 }
905
906 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
907 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
908 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
909 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
910 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
911 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
912 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
913 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
914 #ifdef TARGET_X86_64
915 kvm_getput_reg(&regs.r8, &env->regs[8], set);
916 kvm_getput_reg(&regs.r9, &env->regs[9], set);
917 kvm_getput_reg(&regs.r10, &env->regs[10], set);
918 kvm_getput_reg(&regs.r11, &env->regs[11], set);
919 kvm_getput_reg(&regs.r12, &env->regs[12], set);
920 kvm_getput_reg(&regs.r13, &env->regs[13], set);
921 kvm_getput_reg(&regs.r14, &env->regs[14], set);
922 kvm_getput_reg(&regs.r15, &env->regs[15], set);
923 #endif
924
925 kvm_getput_reg(&regs.rflags, &env->eflags, set);
926 kvm_getput_reg(&regs.rip, &env->eip, set);
927
928 if (set) {
929 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
930 }
931
932 return ret;
933 }
934
935 static int kvm_put_fpu(X86CPU *cpu)
936 {
937 CPUX86State *env = &cpu->env;
938 struct kvm_fpu fpu;
939 int i;
940
941 memset(&fpu, 0, sizeof fpu);
942 fpu.fsw = env->fpus & ~(7 << 11);
943 fpu.fsw |= (env->fpstt & 7) << 11;
944 fpu.fcw = env->fpuc;
945 fpu.last_opcode = env->fpop;
946 fpu.last_ip = env->fpip;
947 fpu.last_dp = env->fpdp;
948 for (i = 0; i < 8; ++i) {
949 fpu.ftwx |= (!env->fptags[i]) << i;
950 }
951 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
952 memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
953 fpu.mxcsr = env->mxcsr;
954
955 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
956 }
957
958 #define XSAVE_FCW_FSW 0
959 #define XSAVE_FTW_FOP 1
960 #define XSAVE_CWD_RIP 2
961 #define XSAVE_CWD_RDP 4
962 #define XSAVE_MXCSR 6
963 #define XSAVE_ST_SPACE 8
964 #define XSAVE_XMM_SPACE 40
965 #define XSAVE_XSTATE_BV 128
966 #define XSAVE_YMMH_SPACE 144
967
968 static int kvm_put_xsave(X86CPU *cpu)
969 {
970 CPUX86State *env = &cpu->env;
971 struct kvm_xsave* xsave = env->kvm_xsave_buf;
972 uint16_t cwd, swd, twd;
973 int i, r;
974
975 if (!kvm_has_xsave()) {
976 return kvm_put_fpu(cpu);
977 }
978
979 memset(xsave, 0, sizeof(struct kvm_xsave));
980 twd = 0;
981 swd = env->fpus & ~(7 << 11);
982 swd |= (env->fpstt & 7) << 11;
983 cwd = env->fpuc;
984 for (i = 0; i < 8; ++i) {
985 twd |= (!env->fptags[i]) << i;
986 }
987 xsave->region[XSAVE_FCW_FSW] = (uint32_t)(swd << 16) + cwd;
988 xsave->region[XSAVE_FTW_FOP] = (uint32_t)(env->fpop << 16) + twd;
989 memcpy(&xsave->region[XSAVE_CWD_RIP], &env->fpip, sizeof(env->fpip));
990 memcpy(&xsave->region[XSAVE_CWD_RDP], &env->fpdp, sizeof(env->fpdp));
991 memcpy(&xsave->region[XSAVE_ST_SPACE], env->fpregs,
992 sizeof env->fpregs);
993 memcpy(&xsave->region[XSAVE_XMM_SPACE], env->xmm_regs,
994 sizeof env->xmm_regs);
995 xsave->region[XSAVE_MXCSR] = env->mxcsr;
996 *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
997 memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
998 sizeof env->ymmh_regs);
999 r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1000 return r;
1001 }
1002
1003 static int kvm_put_xcrs(X86CPU *cpu)
1004 {
1005 CPUX86State *env = &cpu->env;
1006 struct kvm_xcrs xcrs;
1007
1008 if (!kvm_has_xcrs()) {
1009 return 0;
1010 }
1011
1012 xcrs.nr_xcrs = 1;
1013 xcrs.flags = 0;
1014 xcrs.xcrs[0].xcr = 0;
1015 xcrs.xcrs[0].value = env->xcr0;
1016 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1017 }
1018
1019 static int kvm_put_sregs(X86CPU *cpu)
1020 {
1021 CPUX86State *env = &cpu->env;
1022 struct kvm_sregs sregs;
1023
1024 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1025 if (env->interrupt_injected >= 0) {
1026 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1027 (uint64_t)1 << (env->interrupt_injected % 64);
1028 }
1029
1030 if ((env->eflags & VM_MASK)) {
1031 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1032 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1033 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1034 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1035 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1036 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1037 } else {
1038 set_seg(&sregs.cs, &env->segs[R_CS]);
1039 set_seg(&sregs.ds, &env->segs[R_DS]);
1040 set_seg(&sregs.es, &env->segs[R_ES]);
1041 set_seg(&sregs.fs, &env->segs[R_FS]);
1042 set_seg(&sregs.gs, &env->segs[R_GS]);
1043 set_seg(&sregs.ss, &env->segs[R_SS]);
1044 }
1045
1046 set_seg(&sregs.tr, &env->tr);
1047 set_seg(&sregs.ldt, &env->ldt);
1048
1049 sregs.idt.limit = env->idt.limit;
1050 sregs.idt.base = env->idt.base;
1051 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1052 sregs.gdt.limit = env->gdt.limit;
1053 sregs.gdt.base = env->gdt.base;
1054 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1055
1056 sregs.cr0 = env->cr[0];
1057 sregs.cr2 = env->cr[2];
1058 sregs.cr3 = env->cr[3];
1059 sregs.cr4 = env->cr[4];
1060
1061 sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
1062 sregs.apic_base = cpu_get_apic_base(env->apic_state);
1063
1064 sregs.efer = env->efer;
1065
1066 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1067 }
1068
1069 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
1070 uint32_t index, uint64_t value)
1071 {
1072 entry->index = index;
1073 entry->data = value;
1074 }
1075
1076 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1077 {
1078 CPUX86State *env = &cpu->env;
1079 struct {
1080 struct kvm_msrs info;
1081 struct kvm_msr_entry entries[1];
1082 } msr_data;
1083 struct kvm_msr_entry *msrs = msr_data.entries;
1084
1085 if (!has_msr_tsc_deadline) {
1086 return 0;
1087 }
1088
1089 kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1090
1091 msr_data.info.nmsrs = 1;
1092
1093 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1094 }
1095
1096 static int kvm_put_msrs(X86CPU *cpu, int level)
1097 {
1098 CPUX86State *env = &cpu->env;
1099 struct {
1100 struct kvm_msrs info;
1101 struct kvm_msr_entry entries[100];
1102 } msr_data;
1103 struct kvm_msr_entry *msrs = msr_data.entries;
1104 int n = 0, i;
1105
1106 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1107 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1108 kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1109 kvm_msr_entry_set(&msrs[n++], MSR_PAT, env->pat);
1110 if (has_msr_star) {
1111 kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
1112 }
1113 if (has_msr_hsave_pa) {
1114 kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
1115 }
1116 if (has_msr_tsc_adjust) {
1117 kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust);
1118 }
1119 if (has_msr_misc_enable) {
1120 kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE,
1121 env->msr_ia32_misc_enable);
1122 }
1123 #ifdef TARGET_X86_64
1124 if (lm_capable_kernel) {
1125 kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
1126 kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
1127 kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
1128 kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
1129 }
1130 #endif
1131 if (level == KVM_PUT_FULL_STATE) {
1132 /*
1133 * KVM is yet unable to synchronize TSC values of multiple VCPUs on
1134 * writeback. Until this is fixed, we only write the offset to SMP
1135 * guests after migration, desynchronizing the VCPUs, but avoiding
1136 * huge jump-backs that would occur without any writeback at all.
1137 */
1138 if (smp_cpus == 1 || env->tsc != 0) {
1139 kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
1140 }
1141 }
1142 /*
1143 * The following MSRs have side effects on the guest or are too heavy
1144 * for normal writeback. Limit them to reset or full state updates.
1145 */
1146 if (level >= KVM_PUT_RESET_STATE) {
1147 kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
1148 env->system_time_msr);
1149 kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1150 if (has_msr_async_pf_en) {
1151 kvm_msr_entry_set(&msrs[n++], MSR_KVM_ASYNC_PF_EN,
1152 env->async_pf_en_msr);
1153 }
1154 if (has_msr_pv_eoi_en) {
1155 kvm_msr_entry_set(&msrs[n++], MSR_KVM_PV_EOI_EN,
1156 env->pv_eoi_en_msr);
1157 }
1158 if (has_msr_kvm_steal_time) {
1159 kvm_msr_entry_set(&msrs[n++], MSR_KVM_STEAL_TIME,
1160 env->steal_time_msr);
1161 }
1162 if (has_msr_architectural_pmu) {
1163 /* Stop the counter. */
1164 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1165 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL, 0);
1166
1167 /* Set the counter values. */
1168 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1169 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR0 + i,
1170 env->msr_fixed_counters[i]);
1171 }
1172 for (i = 0; i < num_architectural_pmu_counters; i++) {
1173 kvm_msr_entry_set(&msrs[n++], MSR_P6_PERFCTR0 + i,
1174 env->msr_gp_counters[i]);
1175 kvm_msr_entry_set(&msrs[n++], MSR_P6_EVNTSEL0 + i,
1176 env->msr_gp_evtsel[i]);
1177 }
1178 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_STATUS,
1179 env->msr_global_status);
1180 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1181 env->msr_global_ovf_ctrl);
1182
1183 /* Now start the PMU. */
1184 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_FIXED_CTR_CTRL,
1185 env->msr_fixed_ctr_ctrl);
1186 kvm_msr_entry_set(&msrs[n++], MSR_CORE_PERF_GLOBAL_CTRL,
1187 env->msr_global_ctrl);
1188 }
1189 if (hyperv_hypercall_available()) {
1190 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_GUEST_OS_ID, 0);
1191 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_HYPERCALL, 0);
1192 }
1193 if (hyperv_vapic_recommended()) {
1194 kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE, 0);
1195 }
1196 if (has_msr_feature_control) {
1197 kvm_msr_entry_set(&msrs[n++], MSR_IA32_FEATURE_CONTROL,
1198 env->msr_ia32_feature_control);
1199 }
1200 }
1201 if (env->mcg_cap) {
1202 int i;
1203
1204 kvm_msr_entry_set(&msrs[n++], MSR_MCG_STATUS, env->mcg_status);
1205 kvm_msr_entry_set(&msrs[n++], MSR_MCG_CTL, env->mcg_ctl);
1206 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1207 kvm_msr_entry_set(&msrs[n++], MSR_MC0_CTL + i, env->mce_banks[i]);
1208 }
1209 }
1210
1211 msr_data.info.nmsrs = n;
1212
1213 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data);
1214
1215 }
1216
1217
1218 static int kvm_get_fpu(X86CPU *cpu)
1219 {
1220 CPUX86State *env = &cpu->env;
1221 struct kvm_fpu fpu;
1222 int i, ret;
1223
1224 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
1225 if (ret < 0) {
1226 return ret;
1227 }
1228
1229 env->fpstt = (fpu.fsw >> 11) & 7;
1230 env->fpus = fpu.fsw;
1231 env->fpuc = fpu.fcw;
1232 env->fpop = fpu.last_opcode;
1233 env->fpip = fpu.last_ip;
1234 env->fpdp = fpu.last_dp;
1235 for (i = 0; i < 8; ++i) {
1236 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1237 }
1238 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
1239 memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
1240 env->mxcsr = fpu.mxcsr;
1241
1242 return 0;
1243 }
1244
1245 static int kvm_get_xsave(X86CPU *cpu)
1246 {
1247 CPUX86State *env = &cpu->env;
1248 struct kvm_xsave* xsave = env->kvm_xsave_buf;
1249 int ret, i;
1250 uint16_t cwd, swd, twd;
1251
1252 if (!kvm_has_xsave()) {
1253 return kvm_get_fpu(cpu);
1254 }
1255
1256 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
1257 if (ret < 0) {
1258 return ret;
1259 }
1260
1261 cwd = (uint16_t)xsave->region[XSAVE_FCW_FSW];
1262 swd = (uint16_t)(xsave->region[XSAVE_FCW_FSW] >> 16);
1263 twd = (uint16_t)xsave->region[XSAVE_FTW_FOP];
1264 env->fpop = (uint16_t)(xsave->region[XSAVE_FTW_FOP] >> 16);
1265 env->fpstt = (swd >> 11) & 7;
1266 env->fpus = swd;
1267 env->fpuc = cwd;
1268 for (i = 0; i < 8; ++i) {
1269 env->fptags[i] = !((twd >> i) & 1);
1270 }
1271 memcpy(&env->fpip, &xsave->region[XSAVE_CWD_RIP], sizeof(env->fpip));
1272 memcpy(&env->fpdp, &xsave->region[XSAVE_CWD_RDP], sizeof(env->fpdp));
1273 env->mxcsr = xsave->region[XSAVE_MXCSR];
1274 memcpy(env->fpregs, &xsave->region[XSAVE_ST_SPACE],
1275 sizeof env->fpregs);
1276 memcpy(env->xmm_regs, &xsave->region[XSAVE_XMM_SPACE],
1277 sizeof env->xmm_regs);
1278 env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
1279 memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
1280 sizeof env->ymmh_regs);
1281 return 0;
1282 }
1283
1284 static int kvm_get_xcrs(X86CPU *cpu)
1285 {
1286 CPUX86State *env = &cpu->env;
1287 int i, ret;
1288 struct kvm_xcrs xcrs;
1289
1290 if (!kvm_has_xcrs()) {
1291 return 0;
1292 }
1293
1294 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
1295 if (ret < 0) {
1296 return ret;
1297 }
1298
1299 for (i = 0; i < xcrs.nr_xcrs; i++) {
1300 /* Only support xcr0 now */
1301 if (xcrs.xcrs[0].xcr == 0) {
1302 env->xcr0 = xcrs.xcrs[0].value;
1303 break;
1304 }
1305 }
1306 return 0;
1307 }
1308
1309 static int kvm_get_sregs(X86CPU *cpu)
1310 {
1311 CPUX86State *env = &cpu->env;
1312 struct kvm_sregs sregs;
1313 uint32_t hflags;
1314 int bit, i, ret;
1315
1316 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
1317 if (ret < 0) {
1318 return ret;
1319 }
1320
1321 /* There can only be one pending IRQ set in the bitmap at a time, so try
1322 to find it and save its number instead (-1 for none). */
1323 env->interrupt_injected = -1;
1324 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1325 if (sregs.interrupt_bitmap[i]) {
1326 bit = ctz64(sregs.interrupt_bitmap[i]);
1327 env->interrupt_injected = i * 64 + bit;
1328 break;
1329 }
1330 }
1331
1332 get_seg(&env->segs[R_CS], &sregs.cs);
1333 get_seg(&env->segs[R_DS], &sregs.ds);
1334 get_seg(&env->segs[R_ES], &sregs.es);
1335 get_seg(&env->segs[R_FS], &sregs.fs);
1336 get_seg(&env->segs[R_GS], &sregs.gs);
1337 get_seg(&env->segs[R_SS], &sregs.ss);
1338
1339 get_seg(&env->tr, &sregs.tr);
1340 get_seg(&env->ldt, &sregs.ldt);
1341
1342 env->idt.limit = sregs.idt.limit;
1343 env->idt.base = sregs.idt.base;
1344 env->gdt.limit = sregs.gdt.limit;
1345 env->gdt.base = sregs.gdt.base;
1346
1347 env->cr[0] = sregs.cr0;
1348 env->cr[2] = sregs.cr2;
1349 env->cr[3] = sregs.cr3;
1350 env->cr[4] = sregs.cr4;
1351
1352 env->efer = sregs.efer;
1353
1354 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1355
1356 #define HFLAG_COPY_MASK \
1357 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1358 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1359 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1360 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1361
1362 hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
1363 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
1364 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
1365 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
1366 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
1367 hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
1368 (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
1369
1370 if (env->efer & MSR_EFER_LMA) {
1371 hflags |= HF_LMA_MASK;
1372 }
1373
1374 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
1375 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1376 } else {
1377 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
1378 (DESC_B_SHIFT - HF_CS32_SHIFT);
1379 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
1380 (DESC_B_SHIFT - HF_SS32_SHIFT);
1381 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
1382 !(hflags & HF_CS32_MASK)) {
1383 hflags |= HF_ADDSEG_MASK;
1384 } else {
1385 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
1386 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
1387 }
1388 }
1389 env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
1390
1391 return 0;
1392 }
1393
1394 static int kvm_get_msrs(X86CPU *cpu)
1395 {
1396 CPUX86State *env = &cpu->env;
1397 struct {
1398 struct kvm_msrs info;
1399 struct kvm_msr_entry entries[100];
1400 } msr_data;
1401 struct kvm_msr_entry *msrs = msr_data.entries;
1402 int ret, i, n;
1403
1404 n = 0;
1405 msrs[n++].index = MSR_IA32_SYSENTER_CS;
1406 msrs[n++].index = MSR_IA32_SYSENTER_ESP;
1407 msrs[n++].index = MSR_IA32_SYSENTER_EIP;
1408 msrs[n++].index = MSR_PAT;
1409 if (has_msr_star) {
1410 msrs[n++].index = MSR_STAR;
1411 }
1412 if (has_msr_hsave_pa) {
1413 msrs[n++].index = MSR_VM_HSAVE_PA;
1414 }
1415 if (has_msr_tsc_adjust) {
1416 msrs[n++].index = MSR_TSC_ADJUST;
1417 }
1418 if (has_msr_tsc_deadline) {
1419 msrs[n++].index = MSR_IA32_TSCDEADLINE;
1420 }
1421 if (has_msr_misc_enable) {
1422 msrs[n++].index = MSR_IA32_MISC_ENABLE;
1423 }
1424 if (has_msr_feature_control) {
1425 msrs[n++].index = MSR_IA32_FEATURE_CONTROL;
1426 }
1427
1428 if (!env->tsc_valid) {
1429 msrs[n++].index = MSR_IA32_TSC;
1430 env->tsc_valid = !runstate_is_running();
1431 }
1432
1433 #ifdef TARGET_X86_64
1434 if (lm_capable_kernel) {
1435 msrs[n++].index = MSR_CSTAR;
1436 msrs[n++].index = MSR_KERNELGSBASE;
1437 msrs[n++].index = MSR_FMASK;
1438 msrs[n++].index = MSR_LSTAR;
1439 }
1440 #endif
1441 msrs[n++].index = MSR_KVM_SYSTEM_TIME;
1442 msrs[n++].index = MSR_KVM_WALL_CLOCK;
1443 if (has_msr_async_pf_en) {
1444 msrs[n++].index = MSR_KVM_ASYNC_PF_EN;
1445 }
1446 if (has_msr_pv_eoi_en) {
1447 msrs[n++].index = MSR_KVM_PV_EOI_EN;
1448 }
1449 if (has_msr_kvm_steal_time) {
1450 msrs[n++].index = MSR_KVM_STEAL_TIME;
1451 }
1452 if (has_msr_architectural_pmu) {
1453 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR_CTRL;
1454 msrs[n++].index = MSR_CORE_PERF_GLOBAL_CTRL;
1455 msrs[n++].index = MSR_CORE_PERF_GLOBAL_STATUS;
1456 msrs[n++].index = MSR_CORE_PERF_GLOBAL_OVF_CTRL;
1457 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
1458 msrs[n++].index = MSR_CORE_PERF_FIXED_CTR0 + i;
1459 }
1460 for (i = 0; i < num_architectural_pmu_counters; i++) {
1461 msrs[n++].index = MSR_P6_PERFCTR0 + i;
1462 msrs[n++].index = MSR_P6_EVNTSEL0 + i;
1463 }
1464 }
1465
1466 if (env->mcg_cap) {
1467 msrs[n++].index = MSR_MCG_STATUS;
1468 msrs[n++].index = MSR_MCG_CTL;
1469 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
1470 msrs[n++].index = MSR_MC0_CTL + i;
1471 }
1472 }
1473
1474 msr_data.info.nmsrs = n;
1475 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
1476 if (ret < 0) {
1477 return ret;
1478 }
1479
1480 for (i = 0; i < ret; i++) {
1481 uint32_t index = msrs[i].index;
1482 switch (index) {
1483 case MSR_IA32_SYSENTER_CS:
1484 env->sysenter_cs = msrs[i].data;
1485 break;
1486 case MSR_IA32_SYSENTER_ESP:
1487 env->sysenter_esp = msrs[i].data;
1488 break;
1489 case MSR_IA32_SYSENTER_EIP:
1490 env->sysenter_eip = msrs[i].data;
1491 break;
1492 case MSR_PAT:
1493 env->pat = msrs[i].data;
1494 break;
1495 case MSR_STAR:
1496 env->star = msrs[i].data;
1497 break;
1498 #ifdef TARGET_X86_64
1499 case MSR_CSTAR:
1500 env->cstar = msrs[i].data;
1501 break;
1502 case MSR_KERNELGSBASE:
1503 env->kernelgsbase = msrs[i].data;
1504 break;
1505 case MSR_FMASK:
1506 env->fmask = msrs[i].data;
1507 break;
1508 case MSR_LSTAR:
1509 env->lstar = msrs[i].data;
1510 break;
1511 #endif
1512 case MSR_IA32_TSC:
1513 env->tsc = msrs[i].data;
1514 break;
1515 case MSR_TSC_ADJUST:
1516 env->tsc_adjust = msrs[i].data;
1517 break;
1518 case MSR_IA32_TSCDEADLINE:
1519 env->tsc_deadline = msrs[i].data;
1520 break;
1521 case MSR_VM_HSAVE_PA:
1522 env->vm_hsave = msrs[i].data;
1523 break;
1524 case MSR_KVM_SYSTEM_TIME:
1525 env->system_time_msr = msrs[i].data;
1526 break;
1527 case MSR_KVM_WALL_CLOCK:
1528 env->wall_clock_msr = msrs[i].data;
1529 break;
1530 case MSR_MCG_STATUS:
1531 env->mcg_status = msrs[i].data;
1532 break;
1533 case MSR_MCG_CTL:
1534 env->mcg_ctl = msrs[i].data;
1535 break;
1536 case MSR_IA32_MISC_ENABLE:
1537 env->msr_ia32_misc_enable = msrs[i].data;
1538 break;
1539 case MSR_IA32_FEATURE_CONTROL:
1540 env->msr_ia32_feature_control = msrs[i].data;
1541 break;
1542 default:
1543 if (msrs[i].index >= MSR_MC0_CTL &&
1544 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
1545 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
1546 }
1547 break;
1548 case MSR_KVM_ASYNC_PF_EN:
1549 env->async_pf_en_msr = msrs[i].data;
1550 break;
1551 case MSR_KVM_PV_EOI_EN:
1552 env->pv_eoi_en_msr = msrs[i].data;
1553 break;
1554 case MSR_KVM_STEAL_TIME:
1555 env->steal_time_msr = msrs[i].data;
1556 break;
1557 case MSR_CORE_PERF_FIXED_CTR_CTRL:
1558 env->msr_fixed_ctr_ctrl = msrs[i].data;
1559 break;
1560 case MSR_CORE_PERF_GLOBAL_CTRL:
1561 env->msr_global_ctrl = msrs[i].data;
1562 break;
1563 case MSR_CORE_PERF_GLOBAL_STATUS:
1564 env->msr_global_status = msrs[i].data;
1565 break;
1566 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
1567 env->msr_global_ovf_ctrl = msrs[i].data;
1568 break;
1569 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
1570 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
1571 break;
1572 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
1573 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
1574 break;
1575 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
1576 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
1577 break;
1578 }
1579 }
1580
1581 return 0;
1582 }
1583
1584 static int kvm_put_mp_state(X86CPU *cpu)
1585 {
1586 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
1587
1588 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
1589 }
1590
1591 static int kvm_get_mp_state(X86CPU *cpu)
1592 {
1593 CPUState *cs = CPU(cpu);
1594 CPUX86State *env = &cpu->env;
1595 struct kvm_mp_state mp_state;
1596 int ret;
1597
1598 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
1599 if (ret < 0) {
1600 return ret;
1601 }
1602 env->mp_state = mp_state.mp_state;
1603 if (kvm_irqchip_in_kernel()) {
1604 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
1605 }
1606 return 0;
1607 }
1608
1609 static int kvm_get_apic(X86CPU *cpu)
1610 {
1611 CPUX86State *env = &cpu->env;
1612 DeviceState *apic = env->apic_state;
1613 struct kvm_lapic_state kapic;
1614 int ret;
1615
1616 if (apic && kvm_irqchip_in_kernel()) {
1617 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
1618 if (ret < 0) {
1619 return ret;
1620 }
1621
1622 kvm_get_apic_state(apic, &kapic);
1623 }
1624 return 0;
1625 }
1626
1627 static int kvm_put_apic(X86CPU *cpu)
1628 {
1629 CPUX86State *env = &cpu->env;
1630 DeviceState *apic = env->apic_state;
1631 struct kvm_lapic_state kapic;
1632
1633 if (apic && kvm_irqchip_in_kernel()) {
1634 kvm_put_apic_state(apic, &kapic);
1635
1636 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_LAPIC, &kapic);
1637 }
1638 return 0;
1639 }
1640
1641 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
1642 {
1643 CPUX86State *env = &cpu->env;
1644 struct kvm_vcpu_events events;
1645
1646 if (!kvm_has_vcpu_events()) {
1647 return 0;
1648 }
1649
1650 events.exception.injected = (env->exception_injected >= 0);
1651 events.exception.nr = env->exception_injected;
1652 events.exception.has_error_code = env->has_error_code;
1653 events.exception.error_code = env->error_code;
1654 events.exception.pad = 0;
1655
1656 events.interrupt.injected = (env->interrupt_injected >= 0);
1657 events.interrupt.nr = env->interrupt_injected;
1658 events.interrupt.soft = env->soft_interrupt;
1659
1660 events.nmi.injected = env->nmi_injected;
1661 events.nmi.pending = env->nmi_pending;
1662 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
1663 events.nmi.pad = 0;
1664
1665 events.sipi_vector = env->sipi_vector;
1666
1667 events.flags = 0;
1668 if (level >= KVM_PUT_RESET_STATE) {
1669 events.flags |=
1670 KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
1671 }
1672
1673 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
1674 }
1675
1676 static int kvm_get_vcpu_events(X86CPU *cpu)
1677 {
1678 CPUX86State *env = &cpu->env;
1679 struct kvm_vcpu_events events;
1680 int ret;
1681
1682 if (!kvm_has_vcpu_events()) {
1683 return 0;
1684 }
1685
1686 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
1687 if (ret < 0) {
1688 return ret;
1689 }
1690 env->exception_injected =
1691 events.exception.injected ? events.exception.nr : -1;
1692 env->has_error_code = events.exception.has_error_code;
1693 env->error_code = events.exception.error_code;
1694
1695 env->interrupt_injected =
1696 events.interrupt.injected ? events.interrupt.nr : -1;
1697 env->soft_interrupt = events.interrupt.soft;
1698
1699 env->nmi_injected = events.nmi.injected;
1700 env->nmi_pending = events.nmi.pending;
1701 if (events.nmi.masked) {
1702 env->hflags2 |= HF2_NMI_MASK;
1703 } else {
1704 env->hflags2 &= ~HF2_NMI_MASK;
1705 }
1706
1707 env->sipi_vector = events.sipi_vector;
1708
1709 return 0;
1710 }
1711
1712 static int kvm_guest_debug_workarounds(X86CPU *cpu)
1713 {
1714 CPUState *cs = CPU(cpu);
1715 CPUX86State *env = &cpu->env;
1716 int ret = 0;
1717 unsigned long reinject_trap = 0;
1718
1719 if (!kvm_has_vcpu_events()) {
1720 if (env->exception_injected == 1) {
1721 reinject_trap = KVM_GUESTDBG_INJECT_DB;
1722 } else if (env->exception_injected == 3) {
1723 reinject_trap = KVM_GUESTDBG_INJECT_BP;
1724 }
1725 env->exception_injected = -1;
1726 }
1727
1728 /*
1729 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1730 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1731 * by updating the debug state once again if single-stepping is on.
1732 * Another reason to call kvm_update_guest_debug here is a pending debug
1733 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1734 * reinject them via SET_GUEST_DEBUG.
1735 */
1736 if (reinject_trap ||
1737 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
1738 ret = kvm_update_guest_debug(env, reinject_trap);
1739 }
1740 return ret;
1741 }
1742
1743 static int kvm_put_debugregs(X86CPU *cpu)
1744 {
1745 CPUX86State *env = &cpu->env;
1746 struct kvm_debugregs dbgregs;
1747 int i;
1748
1749 if (!kvm_has_debugregs()) {
1750 return 0;
1751 }
1752
1753 for (i = 0; i < 4; i++) {
1754 dbgregs.db[i] = env->dr[i];
1755 }
1756 dbgregs.dr6 = env->dr[6];
1757 dbgregs.dr7 = env->dr[7];
1758 dbgregs.flags = 0;
1759
1760 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
1761 }
1762
1763 static int kvm_get_debugregs(X86CPU *cpu)
1764 {
1765 CPUX86State *env = &cpu->env;
1766 struct kvm_debugregs dbgregs;
1767 int i, ret;
1768
1769 if (!kvm_has_debugregs()) {
1770 return 0;
1771 }
1772
1773 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
1774 if (ret < 0) {
1775 return ret;
1776 }
1777 for (i = 0; i < 4; i++) {
1778 env->dr[i] = dbgregs.db[i];
1779 }
1780 env->dr[4] = env->dr[6] = dbgregs.dr6;
1781 env->dr[5] = env->dr[7] = dbgregs.dr7;
1782
1783 return 0;
1784 }
1785
1786 int kvm_arch_put_registers(CPUState *cpu, int level)
1787 {
1788 X86CPU *x86_cpu = X86_CPU(cpu);
1789 int ret;
1790
1791 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
1792
1793 ret = kvm_getput_regs(x86_cpu, 1);
1794 if (ret < 0) {
1795 return ret;
1796 }
1797 ret = kvm_put_xsave(x86_cpu);
1798 if (ret < 0) {
1799 return ret;
1800 }
1801 ret = kvm_put_xcrs(x86_cpu);
1802 if (ret < 0) {
1803 return ret;
1804 }
1805 ret = kvm_put_sregs(x86_cpu);
1806 if (ret < 0) {
1807 return ret;
1808 }
1809 /* must be before kvm_put_msrs */
1810 ret = kvm_inject_mce_oldstyle(x86_cpu);
1811 if (ret < 0) {
1812 return ret;
1813 }
1814 ret = kvm_put_msrs(x86_cpu, level);
1815 if (ret < 0) {
1816 return ret;
1817 }
1818 if (level >= KVM_PUT_RESET_STATE) {
1819 ret = kvm_put_mp_state(x86_cpu);
1820 if (ret < 0) {
1821 return ret;
1822 }
1823 ret = kvm_put_apic(x86_cpu);
1824 if (ret < 0) {
1825 return ret;
1826 }
1827 }
1828
1829 ret = kvm_put_tscdeadline_msr(x86_cpu);
1830 if (ret < 0) {
1831 return ret;
1832 }
1833
1834 ret = kvm_put_vcpu_events(x86_cpu, level);
1835 if (ret < 0) {
1836 return ret;
1837 }
1838 ret = kvm_put_debugregs(x86_cpu);
1839 if (ret < 0) {
1840 return ret;
1841 }
1842 /* must be last */
1843 ret = kvm_guest_debug_workarounds(x86_cpu);
1844 if (ret < 0) {
1845 return ret;
1846 }
1847 return 0;
1848 }
1849
1850 int kvm_arch_get_registers(CPUState *cs)
1851 {
1852 X86CPU *cpu = X86_CPU(cs);
1853 int ret;
1854
1855 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
1856
1857 ret = kvm_getput_regs(cpu, 0);
1858 if (ret < 0) {
1859 return ret;
1860 }
1861 ret = kvm_get_xsave(cpu);
1862 if (ret < 0) {
1863 return ret;
1864 }
1865 ret = kvm_get_xcrs(cpu);
1866 if (ret < 0) {
1867 return ret;
1868 }
1869 ret = kvm_get_sregs(cpu);
1870 if (ret < 0) {
1871 return ret;
1872 }
1873 ret = kvm_get_msrs(cpu);
1874 if (ret < 0) {
1875 return ret;
1876 }
1877 ret = kvm_get_mp_state(cpu);
1878 if (ret < 0) {
1879 return ret;
1880 }
1881 ret = kvm_get_apic(cpu);
1882 if (ret < 0) {
1883 return ret;
1884 }
1885 ret = kvm_get_vcpu_events(cpu);
1886 if (ret < 0) {
1887 return ret;
1888 }
1889 ret = kvm_get_debugregs(cpu);
1890 if (ret < 0) {
1891 return ret;
1892 }
1893 return 0;
1894 }
1895
1896 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
1897 {
1898 X86CPU *x86_cpu = X86_CPU(cpu);
1899 CPUX86State *env = &x86_cpu->env;
1900 int ret;
1901
1902 /* Inject NMI */
1903 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
1904 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
1905 DPRINTF("injected NMI\n");
1906 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
1907 if (ret < 0) {
1908 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
1909 strerror(-ret));
1910 }
1911 }
1912
1913 if (!kvm_irqchip_in_kernel()) {
1914 /* Force the VCPU out of its inner loop to process any INIT requests
1915 * or pending TPR access reports. */
1916 if (cpu->interrupt_request &
1917 (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
1918 cpu->exit_request = 1;
1919 }
1920
1921 /* Try to inject an interrupt if the guest can accept it */
1922 if (run->ready_for_interrupt_injection &&
1923 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
1924 (env->eflags & IF_MASK)) {
1925 int irq;
1926
1927 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
1928 irq = cpu_get_pic_interrupt(env);
1929 if (irq >= 0) {
1930 struct kvm_interrupt intr;
1931
1932 intr.irq = irq;
1933 DPRINTF("injected interrupt %d\n", irq);
1934 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
1935 if (ret < 0) {
1936 fprintf(stderr,
1937 "KVM: injection failed, interrupt lost (%s)\n",
1938 strerror(-ret));
1939 }
1940 }
1941 }
1942
1943 /* If we have an interrupt but the guest is not ready to receive an
1944 * interrupt, request an interrupt window exit. This will
1945 * cause a return to userspace as soon as the guest is ready to
1946 * receive interrupts. */
1947 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
1948 run->request_interrupt_window = 1;
1949 } else {
1950 run->request_interrupt_window = 0;
1951 }
1952
1953 DPRINTF("setting tpr\n");
1954 run->cr8 = cpu_get_apic_tpr(env->apic_state);
1955 }
1956 }
1957
1958 void kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
1959 {
1960 X86CPU *x86_cpu = X86_CPU(cpu);
1961 CPUX86State *env = &x86_cpu->env;
1962
1963 if (run->if_flag) {
1964 env->eflags |= IF_MASK;
1965 } else {
1966 env->eflags &= ~IF_MASK;
1967 }
1968 cpu_set_apic_tpr(env->apic_state, run->cr8);
1969 cpu_set_apic_base(env->apic_state, run->apic_base);
1970 }
1971
1972 int kvm_arch_process_async_events(CPUState *cs)
1973 {
1974 X86CPU *cpu = X86_CPU(cs);
1975 CPUX86State *env = &cpu->env;
1976
1977 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
1978 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
1979 assert(env->mcg_cap);
1980
1981 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
1982
1983 kvm_cpu_synchronize_state(cs);
1984
1985 if (env->exception_injected == EXCP08_DBLE) {
1986 /* this means triple fault */
1987 qemu_system_reset_request();
1988 cs->exit_request = 1;
1989 return 0;
1990 }
1991 env->exception_injected = EXCP12_MCHK;
1992 env->has_error_code = 0;
1993
1994 cs->halted = 0;
1995 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
1996 env->mp_state = KVM_MP_STATE_RUNNABLE;
1997 }
1998 }
1999
2000 if (kvm_irqchip_in_kernel()) {
2001 return 0;
2002 }
2003
2004 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2005 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
2006 apic_poll_irq(env->apic_state);
2007 }
2008 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2009 (env->eflags & IF_MASK)) ||
2010 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2011 cs->halted = 0;
2012 }
2013 if (cs->interrupt_request & CPU_INTERRUPT_INIT) {
2014 kvm_cpu_synchronize_state(cs);
2015 do_cpu_init(cpu);
2016 }
2017 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
2018 kvm_cpu_synchronize_state(cs);
2019 do_cpu_sipi(cpu);
2020 }
2021 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2022 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
2023 kvm_cpu_synchronize_state(cs);
2024 apic_handle_tpr_access_report(env->apic_state, env->eip,
2025 env->tpr_access_type);
2026 }
2027
2028 return cs->halted;
2029 }
2030
2031 static int kvm_handle_halt(X86CPU *cpu)
2032 {
2033 CPUState *cs = CPU(cpu);
2034 CPUX86State *env = &cpu->env;
2035
2036 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
2037 (env->eflags & IF_MASK)) &&
2038 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2039 cs->halted = 1;
2040 return EXCP_HLT;
2041 }
2042
2043 return 0;
2044 }
2045
2046 static int kvm_handle_tpr_access(X86CPU *cpu)
2047 {
2048 CPUX86State *env = &cpu->env;
2049 CPUState *cs = CPU(cpu);
2050 struct kvm_run *run = cs->kvm_run;
2051
2052 apic_handle_tpr_access_report(env->apic_state, run->tpr_access.rip,
2053 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2054 : TPR_ACCESS_READ);
2055 return 1;
2056 }
2057
2058 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2059 {
2060 static const uint8_t int3 = 0xcc;
2061
2062 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2063 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
2064 return -EINVAL;
2065 }
2066 return 0;
2067 }
2068
2069 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
2070 {
2071 uint8_t int3;
2072
2073 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2074 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
2075 return -EINVAL;
2076 }
2077 return 0;
2078 }
2079
2080 static struct {
2081 target_ulong addr;
2082 int len;
2083 int type;
2084 } hw_breakpoint[4];
2085
2086 static int nb_hw_breakpoint;
2087
2088 static int find_hw_breakpoint(target_ulong addr, int len, int type)
2089 {
2090 int n;
2091
2092 for (n = 0; n < nb_hw_breakpoint; n++) {
2093 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
2094 (hw_breakpoint[n].len == len || len == -1)) {
2095 return n;
2096 }
2097 }
2098 return -1;
2099 }
2100
2101 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2102 target_ulong len, int type)
2103 {
2104 switch (type) {
2105 case GDB_BREAKPOINT_HW:
2106 len = 1;
2107 break;
2108 case GDB_WATCHPOINT_WRITE:
2109 case GDB_WATCHPOINT_ACCESS:
2110 switch (len) {
2111 case 1:
2112 break;
2113 case 2:
2114 case 4:
2115 case 8:
2116 if (addr & (len - 1)) {
2117 return -EINVAL;
2118 }
2119 break;
2120 default:
2121 return -EINVAL;
2122 }
2123 break;
2124 default:
2125 return -ENOSYS;
2126 }
2127
2128 if (nb_hw_breakpoint == 4) {
2129 return -ENOBUFS;
2130 }
2131 if (find_hw_breakpoint(addr, len, type) >= 0) {
2132 return -EEXIST;
2133 }
2134 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2135 hw_breakpoint[nb_hw_breakpoint].len = len;
2136 hw_breakpoint[nb_hw_breakpoint].type = type;
2137 nb_hw_breakpoint++;
2138
2139 return 0;
2140 }
2141
2142 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2143 target_ulong len, int type)
2144 {
2145 int n;
2146
2147 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
2148 if (n < 0) {
2149 return -ENOENT;
2150 }
2151 nb_hw_breakpoint--;
2152 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
2153
2154 return 0;
2155 }
2156
2157 void kvm_arch_remove_all_hw_breakpoints(void)
2158 {
2159 nb_hw_breakpoint = 0;
2160 }
2161
2162 static CPUWatchpoint hw_watchpoint;
2163
2164 static int kvm_handle_debug(X86CPU *cpu,
2165 struct kvm_debug_exit_arch *arch_info)
2166 {
2167 CPUState *cs = CPU(cpu);
2168 CPUX86State *env = &cpu->env;
2169 int ret = 0;
2170 int n;
2171
2172 if (arch_info->exception == 1) {
2173 if (arch_info->dr6 & (1 << 14)) {
2174 if (cs->singlestep_enabled) {
2175 ret = EXCP_DEBUG;
2176 }
2177 } else {
2178 for (n = 0; n < 4; n++) {
2179 if (arch_info->dr6 & (1 << n)) {
2180 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
2181 case 0x0:
2182 ret = EXCP_DEBUG;
2183 break;
2184 case 0x1:
2185 ret = EXCP_DEBUG;
2186 env->watchpoint_hit = &hw_watchpoint;
2187 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2188 hw_watchpoint.flags = BP_MEM_WRITE;
2189 break;
2190 case 0x3:
2191 ret = EXCP_DEBUG;
2192 env->watchpoint_hit = &hw_watchpoint;
2193 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
2194 hw_watchpoint.flags = BP_MEM_ACCESS;
2195 break;
2196 }
2197 }
2198 }
2199 }
2200 } else if (kvm_find_sw_breakpoint(CPU(cpu), arch_info->pc)) {
2201 ret = EXCP_DEBUG;
2202 }
2203 if (ret == 0) {
2204 cpu_synchronize_state(CPU(cpu));
2205 assert(env->exception_injected == -1);
2206
2207 /* pass to guest */
2208 env->exception_injected = arch_info->exception;
2209 env->has_error_code = 0;
2210 }
2211
2212 return ret;
2213 }
2214
2215 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
2216 {
2217 const uint8_t type_code[] = {
2218 [GDB_BREAKPOINT_HW] = 0x0,
2219 [GDB_WATCHPOINT_WRITE] = 0x1,
2220 [GDB_WATCHPOINT_ACCESS] = 0x3
2221 };
2222 const uint8_t len_code[] = {
2223 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2224 };
2225 int n;
2226
2227 if (kvm_sw_breakpoints_active(cpu)) {
2228 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
2229 }
2230 if (nb_hw_breakpoint > 0) {
2231 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
2232 dbg->arch.debugreg[7] = 0x0600;
2233 for (n = 0; n < nb_hw_breakpoint; n++) {
2234 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
2235 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
2236 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
2237 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
2238 }
2239 }
2240 }
2241
2242 static bool host_supports_vmx(void)
2243 {
2244 uint32_t ecx, unused;
2245
2246 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
2247 return ecx & CPUID_EXT_VMX;
2248 }
2249
2250 #define VMX_INVALID_GUEST_STATE 0x80000021
2251
2252 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2253 {
2254 X86CPU *cpu = X86_CPU(cs);
2255 uint64_t code;
2256 int ret;
2257
2258 switch (run->exit_reason) {
2259 case KVM_EXIT_HLT:
2260 DPRINTF("handle_hlt\n");
2261 ret = kvm_handle_halt(cpu);
2262 break;
2263 case KVM_EXIT_SET_TPR:
2264 ret = 0;
2265 break;
2266 case KVM_EXIT_TPR_ACCESS:
2267 ret = kvm_handle_tpr_access(cpu);
2268 break;
2269 case KVM_EXIT_FAIL_ENTRY:
2270 code = run->fail_entry.hardware_entry_failure_reason;
2271 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
2272 code);
2273 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
2274 fprintf(stderr,
2275 "\nIf you're running a guest on an Intel machine without "
2276 "unrestricted mode\n"
2277 "support, the failure can be most likely due to the guest "
2278 "entering an invalid\n"
2279 "state for Intel VT. For example, the guest maybe running "
2280 "in big real mode\n"
2281 "which is not supported on less recent Intel processors."
2282 "\n\n");
2283 }
2284 ret = -1;
2285 break;
2286 case KVM_EXIT_EXCEPTION:
2287 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
2288 run->ex.exception, run->ex.error_code);
2289 ret = -1;
2290 break;
2291 case KVM_EXIT_DEBUG:
2292 DPRINTF("kvm_exit_debug\n");
2293 ret = kvm_handle_debug(cpu, &run->debug.arch);
2294 break;
2295 default:
2296 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
2297 ret = -1;
2298 break;
2299 }
2300
2301 return ret;
2302 }
2303
2304 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
2305 {
2306 X86CPU *cpu = X86_CPU(cs);
2307 CPUX86State *env = &cpu->env;
2308
2309 kvm_cpu_synchronize_state(cs);
2310 return !(env->cr[0] & CR0_PE_MASK) ||
2311 ((env->segs[R_CS].selector & 3) != 3);
2312 }
2313
2314 void kvm_arch_init_irq_routing(KVMState *s)
2315 {
2316 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2317 /* If kernel can't do irq routing, interrupt source
2318 * override 0->2 cannot be set up as required by HPET.
2319 * So we have to disable it.
2320 */
2321 no_hpet = 1;
2322 }
2323 /* We know at this point that we're using the in-kernel
2324 * irqchip, so we can use irqfds, and on x86 we know
2325 * we can use msi via irqfd and GSI routing.
2326 */
2327 kvm_irqfds_allowed = true;
2328 kvm_msi_via_irqfd_allowed = true;
2329 kvm_gsi_routing_allowed = true;
2330 }
2331
2332 /* Classic KVM device assignment interface. Will remain x86 only. */
2333 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
2334 uint32_t flags, uint32_t *dev_id)
2335 {
2336 struct kvm_assigned_pci_dev dev_data = {
2337 .segnr = dev_addr->domain,
2338 .busnr = dev_addr->bus,
2339 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
2340 .flags = flags,
2341 };
2342 int ret;
2343
2344 dev_data.assigned_dev_id =
2345 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
2346
2347 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
2348 if (ret < 0) {
2349 return ret;
2350 }
2351
2352 *dev_id = dev_data.assigned_dev_id;
2353
2354 return 0;
2355 }
2356
2357 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
2358 {
2359 struct kvm_assigned_pci_dev dev_data = {
2360 .assigned_dev_id = dev_id,
2361 };
2362
2363 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
2364 }
2365
2366 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
2367 uint32_t irq_type, uint32_t guest_irq)
2368 {
2369 struct kvm_assigned_irq assigned_irq = {
2370 .assigned_dev_id = dev_id,
2371 .guest_irq = guest_irq,
2372 .flags = irq_type,
2373 };
2374
2375 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
2376 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
2377 } else {
2378 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
2379 }
2380 }
2381
2382 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
2383 uint32_t guest_irq)
2384 {
2385 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
2386 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
2387
2388 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
2389 }
2390
2391 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
2392 {
2393 struct kvm_assigned_pci_dev dev_data = {
2394 .assigned_dev_id = dev_id,
2395 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
2396 };
2397
2398 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
2399 }
2400
2401 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
2402 uint32_t type)
2403 {
2404 struct kvm_assigned_irq assigned_irq = {
2405 .assigned_dev_id = dev_id,
2406 .flags = type,
2407 };
2408
2409 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
2410 }
2411
2412 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
2413 {
2414 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
2415 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
2416 }
2417
2418 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
2419 {
2420 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
2421 KVM_DEV_IRQ_GUEST_MSI, virq);
2422 }
2423
2424 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
2425 {
2426 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
2427 KVM_DEV_IRQ_HOST_MSI);
2428 }
2429
2430 bool kvm_device_msix_supported(KVMState *s)
2431 {
2432 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2433 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2434 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
2435 }
2436
2437 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
2438 uint32_t nr_vectors)
2439 {
2440 struct kvm_assigned_msix_nr msix_nr = {
2441 .assigned_dev_id = dev_id,
2442 .entry_nr = nr_vectors,
2443 };
2444
2445 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
2446 }
2447
2448 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
2449 int virq)
2450 {
2451 struct kvm_assigned_msix_entry msix_entry = {
2452 .assigned_dev_id = dev_id,
2453 .gsi = virq,
2454 .entry = vector,
2455 };
2456
2457 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
2458 }
2459
2460 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
2461 {
2462 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
2463 KVM_DEV_IRQ_GUEST_MSIX, 0);
2464 }
2465
2466 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
2467 {
2468 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
2469 KVM_DEV_IRQ_HOST_MSIX);
2470 }
Qemu copy for testing