/** @file\r
Supporting functions implementaion for PCI devices management.\r
\r
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
+(C) Copyright 2018 Hewlett Packard Enterprise Development LP<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution. The full text of the license may be found at\r
FreePool (PciIoDevice->DevicePath);\r
}\r
\r
+ if (PciIoDevice->BusNumberRanges != NULL) {\r
+ FreePool (PciIoDevice->BusNumberRanges);\r
+ }\r
+\r
FreePool (PciIoDevice);\r
}\r
\r
EFI_STATUS Status;\r
VOID *PlatformOpRomBuffer;\r
UINTN PlatformOpRomSize;\r
- UINT8 PciExpressCapRegOffset;\r
EFI_PCI_IO_PROTOCOL *PciIo;\r
UINT8 Data8;\r
BOOLEAN HasEfiImage;\r
return Status;\r
}\r
\r
- //\r
- // Detect if PCI Express Device\r
- //\r
- PciExpressCapRegOffset = 0;\r
- Status = LocateCapabilityRegBlock (\r
- PciIoDevice,\r
- EFI_PCI_CAPABILITY_ID_PCIEXP,\r
- &PciExpressCapRegOffset,\r
- NULL\r
- );\r
- if (!EFI_ERROR (Status)) {\r
- PciIoDevice->IsPciExp = TRUE;\r
- }\r
-\r
//\r
// Force Interrupt line to "Unknown" or "No Connection"\r
//\r
PciIo = &(PciIoDevice->PciIo);\r
Data8 = PCI_INT_LINE_UNKNOWN;\r
PciIo->Pci.Write (PciIo, EfiPciIoWidthUint8, 0x3C, 1, &Data8);\r
- \r
+\r
//\r
// Process OpRom\r
//\r
PciIoDevice->PciIo.RomImage,\r
PciIoDevice->PciIo.RomSize\r
);\r
- } \r
+ }\r
}\r
}\r
\r
0,\r
&Supports\r
);\r
- //\r
- // By default every bridge's IO and MMIO spaces are enabled.\r
- // Bridge's Bus Master will be enabled when any device behind it requests\r
- // to enable Bus Master.\r
- //\r
- Supports &= (UINT64) (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY);\r
+ Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;\r
PciIoDevice->PciIo.Attributes (\r
&(PciIoDevice->PciIo),\r
EfiPciIoAttributeOperationEnable,\r
0,\r
&Supports\r
);\r
- //\r
- // By default every bridge's IO and MMIO spaces are enabled.\r
- // Bridge's Bus Master will be enabled when any device behind it requests\r
- // to enable Bus Master.\r
- //\r
- Supports &= (UINT64) (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY);\r
+ Supports &= (UINT64)EFI_PCI_DEVICE_ENABLE;\r
PciIoDevice->PciIo.Attributes (\r
&(PciIoDevice->PciIo),\r
EfiPciIoAttributeOperationEnable,\r