+\r
+[PcdsFixedAtBuild.AARCH64]\r
+ #\r
+ # AArch64 Security Extension\r
+ #\r
+\r
+ # Secure Configuration Register\r
+ # - BIT0 : NS - Non Secure bit\r
+ # - BIT1 : IRQ Handler\r
+ # - BIT2 : FIQ Handler\r
+ # - BIT3 : EA - External Abort\r
+ # - BIT4 : FW - F bit writable\r
+ # - BIT5 : AW - A bit writable\r
+ # - BIT6 : nET - Not Early Termination\r
+ # - BIT7 : SCD - Secure Monitor Call Disable\r
+ # - BIT8 : HCE - Hyp Call enable\r
+ # - BIT9 : SIF - Secure Instruction Fetch\r
+ # - BIT10: RW - Register width control for lower exception levels\r
+ # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer\r
+ # - BIT12: TWI - Trap WFI\r
+ # - BIT13: TWE - Trap WFE\r
+ # 0x501 = NS | HCE | RW\r
+ gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038\r
+\r
+ # By default we do transition to EL2 non-secure mode with Stack for EL2.\r
+ # Mode Description Bits\r
+ # NS EL2 SP2 all interrupts disabled = 0x3c9\r
+ # NS EL1 SP1 all interrupts disabled = 0x3c5\r
+ # Other modes include using SP0 or switching to Aarch32, but these are\r
+ # not currently supported.\r
+ gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E\r
+ # If the fixed FDT address is not available, then it should be loaded above the kernel.\r
+ # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB.\r
+ # (see the kernel doc: Documentation/arm64/booting.txt)\r
+ gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023\r
+ # The FDT blob must be loaded at a 2MB aligned address.\r
+ gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026\r
+\r
+\r
+#\r
+# These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be\r
+# redefined when using UEFI in a context of virtual machine.\r
+#\r
+[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common]\r