+// GICv3 specific registers\r
+#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers\r
+\r
+// the Affinity Routing Enable (ARE) bit in GICD_CTLR\r
+#define ARM_GIC_ICDDCR_ARE (1 << 4)\r
+\r
+//\r
+// GIC Redistributor\r
+//\r
+\r
+#define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB\r
+#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB\r
+\r
+// GIC Redistributor Control frame\r
+#define ARM_GICR_TYPER 0x0008 // Redistributor Type Register\r
+\r
+// GIC SGI & PPI Redistributor frame\r
+#define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers\r
+#define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers\r
+\r