ArmPkg/ArmLib: don't invalidate entire I-cache on range operation

[mirror_edk2.git] / ArmPkg / Include / Library / ArmLib.h

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 9effb3eea9bfa96f05addb7b451a27518d5d5e76..4608b0cccccc95785736d406c565da4463ef2674 100644 (file)
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -1,7 +1,7 @@
 /** @file\r
 \r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
 /** @file\r
 \r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r

-  Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>\r
+  Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r

 \r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
 \r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r


@@ -19,41 +19,13 @@
 #include <Uefi/UefiBaseType.h>\r
 \r
 #ifdef MDE_CPU_ARM\r
 #include <Uefi/UefiBaseType.h>\r
 \r
 #ifdef MDE_CPU_ARM\r

-  #ifdef ARM_CPU_ARMv6\r
-    #include <Chipset/ARM1176JZ-S.h>\r
-  #else\r
-    #include <Chipset/ArmV7.h>\r
-  #endif\r
+  #include <Chipset/ArmV7.h>\r

 #elif defined(MDE_CPU_AARCH64)\r
   #include <Chipset/AArch64.h>\r
 #else\r
  #error "Unknown chipset."\r
 #endif\r
 \r
 #elif defined(MDE_CPU_AARCH64)\r
   #include <Chipset/AArch64.h>\r
 #else\r
  #error "Unknown chipset."\r
 #endif\r
 \r

-typedef enum {\r
-  ARM_CACHE_TYPE_WRITE_BACK,\r
-  ARM_CACHE_TYPE_UNKNOWN\r
-} ARM_CACHE_TYPE;\r
-\r
-typedef enum {\r
-  ARM_CACHE_ARCHITECTURE_UNIFIED,\r
-  ARM_CACHE_ARCHITECTURE_SEPARATE,\r
-  ARM_CACHE_ARCHITECTURE_UNKNOWN\r
-} ARM_CACHE_ARCHITECTURE;\r
-\r
-typedef struct {\r
-  ARM_CACHE_TYPE          Type;\r
-  ARM_CACHE_ARCHITECTURE  Architecture;\r
-  BOOLEAN                 DataCachePresent;\r
-  UINTN                   DataCacheSize;\r
-  UINTN                   DataCacheAssociativity;\r
-  UINTN                   DataCacheLineLength;\r
-  BOOLEAN                 InstructionCachePresent;\r
-  UINTN                   InstructionCacheSize;\r
-  UINTN                   InstructionCacheAssociativity;\r
-  UINTN                   InstructionCacheLineLength;\r
-} ARM_CACHE_INFO;\r
-\r

 /**\r
  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
  *\r
 /**\r
  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
  *\r


@@ -130,69 +102,21 @@ typedef enum {
 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))\r
 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
 \r
 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))\r
 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
 \r

-ARM_CACHE_TYPE\r
-EFIAPI\r
-ArmCacheType (\r
-  VOID\r
-  );\r
-\r
-ARM_CACHE_ARCHITECTURE\r
-EFIAPI\r
-ArmCacheArchitecture (\r
-  VOID\r
-  );\r
-\r
-VOID\r
-EFIAPI\r
-ArmCacheInformation (\r
-  OUT ARM_CACHE_INFO  *CacheInfo\r
-  );\r
-\r
-BOOLEAN\r
-EFIAPI\r
-ArmDataCachePresent (\r
-  VOID\r
-  );\r
-\r
-UINTN\r
-EFIAPI\r
-ArmDataCacheSize (\r
-  VOID\r
-  );\r
-\r
-UINTN\r
-EFIAPI\r
-ArmDataCacheAssociativity (\r
-  VOID\r
-  );\r
-\r

 UINTN\r
 EFIAPI\r
 ArmDataCacheLineLength (\r
   VOID\r
   );\r
 \r
 UINTN\r
 EFIAPI\r
 ArmDataCacheLineLength (\r
   VOID\r
   );\r
 \r

-BOOLEAN\r
-EFIAPI\r
-ArmInstructionCachePresent (\r
-  VOID\r
-  );\r
-\r
-UINTN\r
-EFIAPI\r
-ArmInstructionCacheSize (\r
-  VOID\r
-  );\r
-\r

 UINTN\r
 EFIAPI\r
 UINTN\r
 EFIAPI\r

-ArmInstructionCacheAssociativity (\r
+ArmInstructionCacheLineLength (\r

   VOID\r
   );\r
 \r
 UINTN\r
 EFIAPI\r
   VOID\r
   );\r
 \r
 UINTN\r
 EFIAPI\r

-ArmInstructionCacheLineLength (\r
+ArmCacheWritebackGranule (\r

   VOID\r
   );\r
 \r
   VOID\r
   );\r
 \r


@@ -247,28 +171,34 @@ ArmCleanDataCache (
 \r
 VOID\r
 EFIAPI\r
 \r
 VOID\r
 EFIAPI\r

-ArmCleanDataCacheToPoU (\r
+ArmInvalidateInstructionCache (\r

   VOID\r
   );\r
 \r
 VOID\r
 EFIAPI\r
   VOID\r
   );\r
 \r
 VOID\r
 EFIAPI\r

-ArmInvalidateInstructionCache (\r
-  VOID\r
+ArmInvalidateDataCacheEntryByMVA (\r
+  IN  UINTN   Address\r

   );\r
 \r
 VOID\r
 EFIAPI\r
   );\r
 \r
 VOID\r
 EFIAPI\r

-ArmInvalidateDataCacheEntryByMVA (\r
+ArmCleanDataCacheEntryToPoUByMVA (\r

   IN  UINTN   Address\r
   );\r
 \r
 VOID\r
 EFIAPI\r
   IN  UINTN   Address\r
   );\r
 \r
 VOID\r
 EFIAPI\r

-ArmCleanDataCacheEntryByMVA (\r
+ArmInvalidateInstructionCacheEntryToPoUByMVA (\r

   IN  UINTN   Address\r
   );\r
 \r
   IN  UINTN   Address\r
   );\r
 \r

+VOID\r
+EFIAPI\r
+ArmCleanDataCacheEntryByMVA (\r
+IN  UINTN   Address\r
+);\r
+\r

 VOID\r
 EFIAPI\r
 ArmCleanInvalidateDataCacheEntryByMVA (\r
 VOID\r
 EFIAPI\r
 ArmCleanInvalidateDataCacheEntryByMVA (\r


@@ -429,6 +359,12 @@ ArmSetTTBR0 (
   IN  VOID  *TranslationTableBase\r
   );\r
 \r
   IN  VOID  *TranslationTableBase\r
   );\r
 \r

+VOID\r
+EFIAPI\r
+ArmSetTTBCR (\r
+  IN  UINT32 Bits\r
+  );\r
+\r

 VOID *\r
 EFIAPI\r
 ArmGetTTBR0BaseAddress (\r
 VOID *\r
 EFIAPI\r
 ArmGetTTBR0BaseAddress (\r


@@ -473,12 +409,6 @@ ArmSetHighVectors (
   VOID\r
   );\r
 \r
   VOID\r
   );\r
 \r

-VOID\r
-EFIAPI\r
-ArmDrainWriteBuffer (\r
-  VOID\r
-  );\r
-\r

 VOID\r
 EFIAPI\r
 ArmDataMemoryBarrier (\r
 VOID\r
 EFIAPI\r
 ArmDataMemoryBarrier (\r


@@ -487,7 +417,7 @@ ArmDataMemoryBarrier (
 \r
 VOID\r
 EFIAPI\r
 \r
 VOID\r
 EFIAPI\r

-ArmDataSyncronizationBarrier (\r
+ArmDataSynchronizationBarrier (\r

   VOID\r
   );\r
 \r
   VOID\r
   );\r
 \r


@@ -665,4 +595,34 @@ ArmUnsetCpuActlrBit (
   IN  UINTN    Bits\r
   );\r
 \r
   IN  UINTN    Bits\r
   );\r
 \r

+RETURN_STATUS\r
+ArmSetMemoryRegionNoExec (\r
+  IN  EFI_PHYSICAL_ADDRESS      BaseAddress,\r
+  IN  UINT64                    Length\r
+  );\r
+\r
+RETURN_STATUS\r
+ArmClearMemoryRegionNoExec (\r
+  IN  EFI_PHYSICAL_ADDRESS      BaseAddress,\r
+  IN  UINT64                    Length\r
+  );\r
+\r
+RETURN_STATUS\r
+ArmSetMemoryRegionReadOnly (\r
+  IN  EFI_PHYSICAL_ADDRESS      BaseAddress,\r
+  IN  UINT64                    Length\r
+  );\r
+\r
+RETURN_STATUS\r
+ArmClearMemoryRegionReadOnly (\r
+  IN  EFI_PHYSICAL_ADDRESS      BaseAddress,\r
+  IN  UINT64                    Length\r
+  );\r
+\r
+VOID\r
+ArmReplaceLiveTranslationEntry (\r
+  IN  UINT64  *Entry,\r
+  IN  UINT64  Value\r
+  );\r
+\r

 #endif // __ARM_LIB__\r
 #endif // __ARM_LIB__\r