ArmPkg/Include/Library/ArmLib.h

   1 /** @file
   2
   3   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4   Copyright (c) 2011 - 2015, ARM Ltd. All rights reserved.<BR>
   5
   6   This program and the accompanying materials
   7   are licensed and made available under the terms and conditions of the BSD License
   8   which accompanies this distribution.  The full text of the license may be found at
   9   http://opensource.org/licenses/bsd-license.php
  10
  11   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13
  14 **/
  15
  16 #ifndef __ARM_LIB__
  17 #define __ARM_LIB__
  18
  19 #include <Uefi/UefiBaseType.h>
  20
  21 #ifdef MDE_CPU_ARM
  22   #ifdef ARM_CPU_ARMv6
  23     #include <Chipset/ARM1176JZ-S.h>
  24   #else
  25     #include <Chipset/ArmV7.h>
  26   #endif
  27 #elif defined(MDE_CPU_AARCH64)
  28   #include <Chipset/AArch64.h>
  29 #else
  30  #error "Unknown chipset."
  31 #endif
  32
  33 typedef enum {
  34   ARM_CACHE_TYPE_WRITE_BACK,
  35   ARM_CACHE_TYPE_UNKNOWN
  36 } ARM_CACHE_TYPE;
  37
  38 typedef enum {
  39   ARM_CACHE_ARCHITECTURE_UNIFIED,
  40   ARM_CACHE_ARCHITECTURE_SEPARATE,
  41   ARM_CACHE_ARCHITECTURE_UNKNOWN
  42 } ARM_CACHE_ARCHITECTURE;
  43
  44 typedef struct {
  45   ARM_CACHE_TYPE          Type;
  46   ARM_CACHE_ARCHITECTURE  Architecture;
  47   BOOLEAN                 DataCachePresent;
  48   UINTN                   DataCacheSize;
  49   UINTN                   DataCacheAssociativity;
  50   UINTN                   DataCacheLineLength;
  51   BOOLEAN                 InstructionCachePresent;
  52   UINTN                   InstructionCacheSize;
  53   UINTN                   InstructionCacheAssociativity;
  54   UINTN                   InstructionCacheLineLength;
  55 } ARM_CACHE_INFO;
  56
  57 /**
  58  * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.
  59  *
  60  * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only
  61  * be used in Secure World to distinguished Secure to Non-Secure memory.
  62  */
  63 typedef enum {
  64   ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,
  65   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,
  66   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
  67   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,
  68   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
  69   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,
  70   ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,
  71   ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
  72 } ARM_MEMORY_REGION_ATTRIBUTES;
  73
  74 #define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
  75
  76 typedef struct {
  77   EFI_PHYSICAL_ADDRESS          PhysicalBase;
  78   EFI_VIRTUAL_ADDRESS           VirtualBase;
  79   UINT64                        Length;
  80   ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
  81 } ARM_MEMORY_REGION_DESCRIPTOR;
  82
  83 typedef VOID (*CACHE_OPERATION)(VOID);
  84 typedef VOID (*LINE_OPERATION)(UINTN);
  85
  86 //
  87 // ARM Processor Mode
  88 //
  89 typedef enum {
  90   ARM_PROCESSOR_MODE_USER       = 0x10,
  91   ARM_PROCESSOR_MODE_FIQ        = 0x11,
  92   ARM_PROCESSOR_MODE_IRQ        = 0x12,
  93   ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
  94   ARM_PROCESSOR_MODE_ABORT      = 0x17,
  95   ARM_PROCESSOR_MODE_HYP        = 0x1A,
  96   ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
  97   ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
  98   ARM_PROCESSOR_MODE_MASK       = 0x1F
  99 } ARM_PROCESSOR_MODE;
 100
 101 //
 102 // ARM Cpu IDs
 103 //
 104 #define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)
 105 #define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)
 106 #define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)
 107 #define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)
 108 #define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)
 109 #define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)
 110
 111 #define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)
 112 #define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)
 113 #define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)
 114 #define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)
 115 #define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)
 116 #define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)
 117
 118 //
 119 // ARM MP Core IDs
 120 //
 121 #define ARM_CORE_AFF0         0xFF
 122 #define ARM_CORE_AFF1         (0xFF << 8)
 123 #define ARM_CORE_AFF2         (0xFF << 16)
 124 #define ARM_CORE_AFF3         (0xFFULL << 32)
 125
 126 #define ARM_CORE_MASK         ARM_CORE_AFF0
 127 #define ARM_CLUSTER_MASK      ARM_CORE_AFF1
 128 #define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)
 129 #define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)
 130 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))
 131 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
 132
 133 ARM_CACHE_TYPE
 134 EFIAPI
 135 ArmCacheType (
 136   VOID
 137   );
 138
 139 ARM_CACHE_ARCHITECTURE
 140 EFIAPI
 141 ArmCacheArchitecture (
 142   VOID
 143   );
 144
 145 VOID
 146 EFIAPI
 147 ArmCacheInformation (
 148   OUT ARM_CACHE_INFO  *CacheInfo
 149   );
 150
 151 BOOLEAN
 152 EFIAPI
 153 ArmDataCachePresent (
 154   VOID
 155   );
 156
 157 UINTN
 158 EFIAPI
 159 ArmDataCacheSize (
 160   VOID
 161   );
 162
 163 UINTN
 164 EFIAPI
 165 ArmDataCacheAssociativity (
 166   VOID
 167   );
 168
 169 UINTN
 170 EFIAPI
 171 ArmDataCacheLineLength (
 172   VOID
 173   );
 174
 175 BOOLEAN
 176 EFIAPI
 177 ArmInstructionCachePresent (
 178   VOID
 179   );
 180
 181 UINTN
 182 EFIAPI
 183 ArmInstructionCacheSize (
 184   VOID
 185   );
 186
 187 UINTN
 188 EFIAPI
 189 ArmInstructionCacheAssociativity (
 190   VOID
 191   );
 192
 193 UINTN
 194 EFIAPI
 195 ArmInstructionCacheLineLength (
 196   VOID
 197   );
 198
 199 UINTN
 200 EFIAPI
 201 ArmIsArchTimerImplemented (
 202   VOID
 203   );
 204
 205 UINTN
 206 EFIAPI
 207 ArmReadIdPfr0 (
 208   VOID
 209   );
 210
 211 UINTN
 212 EFIAPI
 213 ArmReadIdPfr1 (
 214   VOID
 215   );
 216
 217 UINTN
 218 EFIAPI
 219 ArmCacheInfo (
 220   VOID
 221   );
 222
 223 BOOLEAN
 224 EFIAPI
 225 ArmIsMpCore (
 226   VOID
 227   );
 228
 229 VOID
 230 EFIAPI
 231 ArmInvalidateDataCache (
 232   VOID
 233   );
 234
 235
 236 VOID
 237 EFIAPI
 238 ArmCleanInvalidateDataCache (
 239   VOID
 240   );
 241
 242 VOID
 243 EFIAPI
 244 ArmCleanDataCache (
 245   VOID
 246   );
 247
 248 VOID
 249 EFIAPI
 250 ArmCleanDataCacheToPoU (
 251   VOID
 252   );
 253
 254 VOID
 255 EFIAPI
 256 ArmInvalidateInstructionCache (
 257   VOID
 258   );
 259
 260 VOID
 261 EFIAPI
 262 ArmInvalidateDataCacheEntryByMVA (
 263   IN  UINTN   Address
 264   );
 265
 266 VOID
 267 EFIAPI
 268 ArmCleanDataCacheEntryByMVA (
 269   IN  UINTN   Address
 270   );
 271
 272 VOID
 273 EFIAPI
 274 ArmCleanInvalidateDataCacheEntryByMVA (
 275   IN  UINTN   Address
 276   );
 277
 278 VOID
 279 EFIAPI
 280 ArmInvalidateDataCacheEntryBySetWay (
 281   IN  UINTN  SetWayFormat
 282   );
 283
 284 VOID
 285 EFIAPI
 286 ArmCleanDataCacheEntryBySetWay (
 287   IN  UINTN  SetWayFormat
 288   );
 289
 290 VOID
 291 EFIAPI
 292 ArmCleanInvalidateDataCacheEntryBySetWay (
 293   IN  UINTN   SetWayFormat
 294   );
 295
 296 VOID
 297 EFIAPI
 298 ArmEnableDataCache (
 299   VOID
 300   );
 301
 302 VOID
 303 EFIAPI
 304 ArmDisableDataCache (
 305   VOID
 306   );
 307
 308 VOID
 309 EFIAPI
 310 ArmEnableInstructionCache (
 311   VOID
 312   );
 313
 314 VOID
 315 EFIAPI
 316 ArmDisableInstructionCache (
 317   VOID
 318   );
 319
 320 VOID
 321 EFIAPI
 322 ArmEnableMmu (
 323   VOID
 324   );
 325
 326 VOID
 327 EFIAPI
 328 ArmDisableMmu (
 329   VOID
 330   );
 331
 332 VOID
 333 EFIAPI
 334 ArmEnableCachesAndMmu (
 335   VOID
 336   );
 337
 338 VOID
 339 EFIAPI
 340 ArmDisableCachesAndMmu (
 341   VOID
 342   );
 343
 344 VOID
 345 EFIAPI
 346 ArmEnableInterrupts (
 347   VOID
 348   );
 349
 350 UINTN
 351 EFIAPI
 352 ArmDisableInterrupts (
 353   VOID
 354   );
 355
 356 BOOLEAN
 357 EFIAPI
 358 ArmGetInterruptState (
 359   VOID
 360   );
 361
 362 VOID
 363 EFIAPI
 364 ArmEnableAsynchronousAbort (
 365   VOID
 366   );
 367
 368 UINTN
 369 EFIAPI
 370 ArmDisableAsynchronousAbort (
 371   VOID
 372   );
 373
 374 VOID
 375 EFIAPI
 376 ArmEnableIrq (
 377   VOID
 378   );
 379
 380 UINTN
 381 EFIAPI
 382 ArmDisableIrq (
 383   VOID
 384   );
 385
 386 VOID
 387 EFIAPI
 388 ArmEnableFiq (
 389   VOID
 390   );
 391
 392 UINTN
 393 EFIAPI
 394 ArmDisableFiq (
 395   VOID
 396   );
 397
 398 BOOLEAN
 399 EFIAPI
 400 ArmGetFiqState (
 401   VOID
 402   );
 403
 404 /**
 405  * Invalidate Data and Instruction TLBs
 406  */
 407 VOID
 408 EFIAPI
 409 ArmInvalidateTlb (
 410   VOID
 411   );
 412
 413 VOID
 414 EFIAPI
 415 ArmUpdateTranslationTableEntry (
 416   IN  VOID     *TranslationTableEntry,
 417   IN  VOID     *Mva
 418   );
 419
 420 VOID
 421 EFIAPI
 422 ArmSetDomainAccessControl (
 423   IN  UINT32  Domain
 424   );
 425
 426 VOID
 427 EFIAPI
 428 ArmSetTTBR0 (
 429   IN  VOID  *TranslationTableBase
 430   );
 431
 432 VOID *
 433 EFIAPI
 434 ArmGetTTBR0BaseAddress (
 435   VOID
 436   );
 437
 438 RETURN_STATUS
 439 EFIAPI
 440 ArmConfigureMmu (
 441   IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
 442   OUT VOID                         **TranslationTableBase OPTIONAL,
 443   OUT UINTN                         *TranslationTableSize  OPTIONAL
 444   );
 445
 446 BOOLEAN
 447 EFIAPI
 448 ArmMmuEnabled (
 449   VOID
 450   );
 451
 452 VOID
 453 EFIAPI
 454 ArmEnableBranchPrediction (
 455   VOID
 456   );
 457
 458 VOID
 459 EFIAPI
 460 ArmDisableBranchPrediction (
 461   VOID
 462   );
 463
 464 VOID
 465 EFIAPI
 466 ArmSetLowVectors (
 467   VOID
 468   );
 469
 470 VOID
 471 EFIAPI
 472 ArmSetHighVectors (
 473   VOID
 474   );
 475
 476 VOID
 477 EFIAPI
 478 ArmDrainWriteBuffer (
 479   VOID
 480   );
 481
 482 VOID
 483 EFIAPI
 484 ArmDataMemoryBarrier (
 485   VOID
 486   );
 487
 488 VOID
 489 EFIAPI
 490 ArmDataSyncronizationBarrier (
 491   VOID
 492   );
 493
 494 VOID
 495 EFIAPI
 496 ArmInstructionSynchronizationBarrier (
 497   VOID
 498   );
 499
 500 VOID
 501 EFIAPI
 502 ArmWriteVBar (
 503   IN  UINTN   VectorBase
 504   );
 505
 506 UINTN
 507 EFIAPI
 508 ArmReadVBar (
 509   VOID
 510   );
 511
 512 VOID
 513 EFIAPI
 514 ArmWriteAuxCr (
 515   IN  UINT32    Bit
 516   );
 517
 518 UINT32
 519 EFIAPI
 520 ArmReadAuxCr (
 521   VOID
 522   );
 523
 524 VOID
 525 EFIAPI
 526 ArmSetAuxCrBit (
 527   IN  UINT32    Bits
 528   );
 529
 530 VOID
 531 EFIAPI
 532 ArmUnsetAuxCrBit (
 533   IN  UINT32    Bits
 534   );
 535
 536 VOID
 537 EFIAPI
 538 ArmCallSEV (
 539   VOID
 540   );
 541
 542 VOID
 543 EFIAPI
 544 ArmCallWFE (
 545   VOID
 546   );
 547
 548 VOID
 549 EFIAPI
 550 ArmCallWFI (
 551
 552   VOID
 553   );
 554
 555 UINTN
 556 EFIAPI
 557 ArmReadMpidr (
 558   VOID
 559   );
 560
 561 UINTN
 562 EFIAPI
 563 ArmReadMidr (
 564   VOID
 565   );
 566
 567 UINT32
 568 EFIAPI
 569 ArmReadCpacr (
 570   VOID
 571   );
 572
 573 VOID
 574 EFIAPI
 575 ArmWriteCpacr (
 576   IN  UINT32   Access
 577   );
 578
 579 VOID
 580 EFIAPI
 581 ArmEnableVFP (
 582   VOID
 583   );
 584
 585 /**
 586   Get the Secure Configuration Register value
 587
 588   @return   Value read from the Secure Configuration Register
 589
 590 **/
 591 UINT32
 592 EFIAPI
 593 ArmReadScr (
 594   VOID
 595   );
 596
 597 /**
 598   Set the Secure Configuration Register
 599
 600   @param Value   Value to write to the Secure Configuration Register
 601
 602 **/
 603 VOID
 604 EFIAPI
 605 ArmWriteScr (
 606   IN  UINT32   Value
 607   );
 608
 609 UINT32
 610 EFIAPI
 611 ArmReadMVBar (
 612   VOID
 613   );
 614
 615 VOID
 616 EFIAPI
 617 ArmWriteMVBar (
 618   IN  UINT32   VectorMonitorBase
 619   );
 620
 621 UINT32
 622 EFIAPI
 623 ArmReadSctlr (
 624   VOID
 625   );
 626
 627 UINTN
 628 EFIAPI
 629 ArmReadHVBar (
 630   VOID
 631   );
 632
 633 VOID
 634 EFIAPI
 635 ArmWriteHVBar (
 636   IN  UINTN   HypModeVectorBase
 637   );
 638
 639
 640 //
 641 // Helper functions for accessing CPU ACTLR
 642 //
 643
 644 UINTN
 645 EFIAPI
 646 ArmReadCpuActlr (
 647   VOID
 648   );
 649
 650 VOID
 651 EFIAPI
 652 ArmWriteCpuActlr (
 653   IN  UINTN Val
 654   );
 655
 656 VOID
 657 EFIAPI
 658 ArmSetCpuActlrBit (
 659   IN  UINTN    Bits
 660   );
 661
 662 VOID
 663 EFIAPI
 664 ArmUnsetCpuActlrBit (
 665   IN  UINTN    Bits
 666   );
 667
 668 #endif // __ARM_LIB__