- b Loop1\r
-\r
-ASM_PFX(AArch64PerformPoUDataCacheOperation):\r
-// We can use regs 0-7 and 9-15 without having to save/restore.\r
-// Save our link register on the stack.\r
- str x30, [sp, #-0x10]!\r
- mov x1, x0 // Save Function call in x1\r
- mrs x6, clidr_el1 // Read EL1 CLIDR\r
- and x3, x6, #0x38000000 // Mask out all but Point of Unification (PoU)\r
- lsr x3, x3, #26 // Left align cache level value - the level is shifted by 1 to the\r
- // right to ease the access to CSSELR and the Set/Way operation.\r
- cbz x3, L_Finished // No need to clean if LoC is 0\r
- mov x10, #0 // Start clean at cache level 0\r