add R2, R10, R10, LSR #1 ; Work out 3xcachelevel\r
mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level\r
and R12, R12, #7 ; get those 3 bits alone\r
cmp R12, #2\r
blt Skip2 ; no cache or only instruction cache at this level\r
mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
add R2, R10, R10, LSR #1 ; Work out 3xcachelevel\r
mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level\r
and R12, R12, #7 ; get those 3 bits alone\r
cmp R12, #2\r
blt Skip2 ; no cache or only instruction cache at this level\r
mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r