MdeModulePkg/PciBusDxe: Fix small memory leak in FreePciDevice

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciPei / XhcPeim.h

diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h
index 3b77f2aba7ab3e45f0d9030d3bb5f42c792777c3..e7a100f2971d6de8d9cbae1ae27ecd23ce8dad6f 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h
+++ b/MdeModulePkg/Bus/Pci/XhciPei/XhcPeim.h
@@ -1,7 +1,7 @@
 /** @file\r
 Private Header file for Usb Host Controller PEIM\r
 \r
 /** @file\r
 Private Header file for Usb Host Controller PEIM\r
 \r

-Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>\r

 \r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions\r
 \r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions\r


@@ -21,6 +21,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 \r
 #include <Ppi/UsbController.h>\r
 #include <Ppi/Usb2HostController.h>\r
 \r
 #include <Ppi/UsbController.h>\r
 #include <Ppi/Usb2HostController.h>\r

+#include <Ppi/IoMmu.h>\r
+#include <Ppi/EndOfPeiPhase.h>\r

 \r
 #include <Library/DebugLib.h>\r
 #include <Library/PeimEntryPoint.h>\r
 \r
 #include <Library/DebugLib.h>\r
 #include <Library/PeimEntryPoint.h>\r


@@ -48,21 +50,26 @@ typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;
 \r
 //\r
 // XHC reset timeout experience values.\r
 \r
 //\r
 // XHC reset timeout experience values.\r

-// The unit is microsecond, setting it as 1s.\r
+// The unit is millisecond, setting it as 1s.\r

 //\r
 //\r

-#define XHC_RESET_TIMEOUT           (1 * XHC_1_SECOND)\r
+#define XHC_RESET_TIMEOUT           (1000)\r
+\r

 //\r
 //\r

-// XHC delay experience value for polling operation.\r
-// The unit is microsecond, set it as 1ms.\r
+// TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5.\r
+// The unit is microsecond, setting it as 10ms.\r

 //\r
 //\r

-#define XHC_POLL_DELAY              (1 * XHC_1_MILLISECOND)\r
+#define XHC_RESET_RECOVERY_DELAY     (10 * 1000)\r

 \r
 //\r
 // Wait for root port state stable.\r
 //\r
 #define XHC_ROOT_PORT_STATE_STABLE  (200 * XHC_1_MILLISECOND)\r
 \r
 \r
 //\r
 // Wait for root port state stable.\r
 //\r
 #define XHC_ROOT_PORT_STATE_STABLE  (200 * XHC_1_MILLISECOND)\r
 \r

-#define XHC_GENERIC_TIMEOUT         (10 * XHC_1_MILLISECOND)\r
+//\r
+// XHC generic timeout experience values.\r
+// The unit is millisecond, setting it as 10s.\r
+//\r
+#define XHC_GENERIC_TIMEOUT         (10 * 1000)\r

 \r
 #define XHC_LOW_32BIT(Addr64)       ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))\r
 #define XHC_HIGH_32BIT(Addr64)      ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r
 \r
 #define XHC_LOW_32BIT(Addr64)       ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))\r
 #define XHC_HIGH_32BIT(Addr64)      ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r


@@ -147,6 +154,12 @@ struct _PEI_XHC_DEV {
   UINT32                            UsbHostControllerBaseAddress;\r
   USBHC_MEM_POOL                    *MemPool;\r
 \r
   UINT32                            UsbHostControllerBaseAddress;\r
   USBHC_MEM_POOL                    *MemPool;\r
 \r

+  //\r
+  // EndOfPei callback is used to stop the XHC DMA operation\r
+  // after exit PEI phase.\r
+  //\r
+  EFI_PEI_NOTIFY_DESCRIPTOR         EndOfPeiNotifyList;\r
+\r

   //\r
   // XHCI configuration data\r
   //\r
   //\r
   // XHCI configuration data\r
   //\r


@@ -159,7 +172,9 @@ struct _PEI_XHC_DEV {
   UINT32                            PageSize;\r
   UINT32                            MaxScratchpadBufs;\r
   UINT64                            *ScratchBuf;\r
   UINT32                            PageSize;\r
   UINT32                            MaxScratchpadBufs;\r
   UINT64                            *ScratchBuf;\r

+  VOID                              *ScratchMap;\r

   UINT64                            *ScratchEntry;\r
   UINT64                            *ScratchEntry;\r

+  UINTN                             *ScratchEntryMap;\r

   UINT64                            *DCBAA;\r
   UINT32                            MaxSlotsEn;\r
   //\r
   UINT64                            *DCBAA;\r
   UINT32                            MaxSlotsEn;\r
   //\r


@@ -179,6 +194,7 @@ struct _PEI_XHC_DEV {
 };\r
 \r
 #define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS(a) CR (a, PEI_XHC_DEV, Usb2HostControllerPpi, USB_XHC_DEV_SIGNATURE)\r
 };\r
 \r
 #define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS(a) CR (a, PEI_XHC_DEV, Usb2HostControllerPpi, USB_XHC_DEV_SIGNATURE)\r

+#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_XHC_DEV, EndOfPeiNotifyList, USB_XHC_DEV_SIGNATURE)\r

 \r
 /**\r
   Initialize the memory management pool for the host controller.\r
 \r
 /**\r
   Initialize the memory management pool for the host controller.\r


@@ -237,4 +253,100 @@ UsbHcFreeMem (
   )\r
 ;\r
 \r
   )\r
 ;\r
 \r

+\r
+/**\r
+  Initialize IOMMU.\r
+**/\r
+VOID\r
+IoMmuInit (\r
+  VOID\r
+  );\r
+\r
+/**\r
+  Provides the controller-specific addresses required to access system memory from a\r
+  DMA bus master.\r
+\r
+  @param  Operation             Indicates if the bus master is going to read or write to system memory.\r
+  @param  HostAddress           The system memory address to map to the PCI controller.\r
+  @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes\r
+                                that were mapped.\r
+  @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to\r
+                                access the hosts HostAddress.\r
+  @param  Mapping               A resulting value to pass to Unmap().\r
+\r
+  @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.\r
+  @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.\r
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
+  @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.\r
+\r
+**/\r
+EFI_STATUS\r
+IoMmuMap (\r
+  IN  EDKII_IOMMU_OPERATION Operation,\r
+  IN  VOID                  *HostAddress,\r
+  IN  OUT UINTN             *NumberOfBytes,\r
+  OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,\r
+  OUT VOID                  **Mapping\r
+  );\r
+\r
+/**\r
+  Completes the Map() operation and releases any corresponding resources.\r
+\r
+  @param  Mapping               The mapping value returned from Map().\r
+\r
+  @retval EFI_SUCCESS           The range was unmapped.\r
+  @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
+  @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.\r
+**/\r
+EFI_STATUS\r
+IoMmuUnmap (\r
+  IN VOID                  *Mapping\r
+  );\r
+\r
+/**\r
+  Allocates pages that are suitable for an OperationBusMasterCommonBuffer or\r
+  OperationBusMasterCommonBuffer64 mapping.\r
+\r
+  @param  Pages                 The number of pages to allocate.\r
+  @param  HostAddress           A pointer to store the base system memory address of the\r
+                                allocated range.\r
+  @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to\r
+                                access the hosts HostAddress.\r
+  @param  Mapping               A resulting value to pass to Unmap().\r
+\r
+  @retval EFI_SUCCESS           The requested memory pages were allocated.\r
+  @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are\r
+                                MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
+  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
+  @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.\r
+\r
+**/\r
+EFI_STATUS\r
+IoMmuAllocateBuffer (\r
+  IN UINTN                  Pages,\r
+  OUT VOID                  **HostAddress,\r
+  OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,\r
+  OUT VOID                  **Mapping\r
+  );\r
+\r
+/**\r
+  Frees memory that was allocated with AllocateBuffer().\r
+\r
+  @param  Pages                 The number of pages to free.\r
+  @param  HostAddress           The base system memory address of the allocated range.\r
+  @param  Mapping               The mapping value returned from Map().\r
+\r
+  @retval EFI_SUCCESS           The requested memory pages were freed.\r
+  @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
+                                was not allocated with AllocateBuffer().\r
+\r
+**/\r
+EFI_STATUS\r
+IoMmuFreeBuffer (\r
+  IN UINTN                  Pages,\r
+  IN VOID                   *HostAddress,\r
+  IN VOID                   *Mapping\r
+  );\r
+\r

 #endif\r
 #endif\r