The PAL procedure supports the Static Registers calling\r
convention. It could be called at virtual mode and physical\r
mode.\r
The PAL procedure supports the Static Registers calling\r
convention. It could be called at virtual mode and physical\r
mode.\r
convention. It could be called at physical mode.\r
\r
@param Index Index of PAL_CACHE_INIT within the list of PAL\r
convention. It could be called at physical mode.\r
\r
@param Index Index of PAL_CACHE_INIT within the list of PAL\r
PAL Procedure - PAL_CACHE_PROT_INFO.\r
\r
Return instruction or data cache protection information. It is\r
PAL Procedure - PAL_CACHE_PROT_INFO.\r
\r
Return instruction or data cache protection information. It is\r
\r
Used in architected sequence to transition pages from a\r
cacheable, speculative attribute to an uncacheable attribute.\r
\r
Used in architected sequence to transition pages from a\r
cacheable, speculative attribute to an uncacheable attribute.\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and Virtual mode.\r
\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and Virtual mode.\r
\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and Virtual mode.\r
\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and Virtual mode.\r
\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and Virtual mode.\r
\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and Virtual mode.\r
\r
convention. It could be called at physical mode.\r
\r
@param Index Index of PAL_VM_TR_READ within the list\r
convention. It could be called at physical mode.\r
\r
@param Index Index of PAL_VM_TR_READ within the list\r
PAL Procedure - PAL_BUS_GET_FEATURES.\r
\r
Return configurable processor bus interface features and their\r
PAL Procedure - PAL_BUS_GET_FEATURES.\r
\r
Return configurable processor bus interface features and their\r
PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode and virtual\r
mode.\r
PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode and virtual\r
mode.\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and virtual mode.\r
\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and virtual mode.\r
\r
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Return ratio of processor, bus, and interval time counter to\r
processor input clock or output clock for platform use, if\r
\r
Return ratio of processor, bus, and interval time counter to\r
processor input clock or output clock for platform use, if\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and virtual mode.\r
\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and virtual mode.\r
\r
The PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode and virtual\r
mode.\r
The PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode and virtual\r
mode.\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and virtual mode.\r
\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and virtual mode.\r
\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and virtual mode.\r
\r
procedure supports the Static Registers calling convention. It\r
could be called at physical mode and virtual mode.\r
\r
PAL procedure supports the Static Registers calling\r
convention. It could be called at physical and virtual mode.\r
\r
PAL procedure supports the Static Registers calling\r
convention. It could be called at physical and virtual mode.\r
\r
convention. It could be called at physical mode.\r
\r
@param Index Index of PAL_MC_EXPECTED within the list of PAL\r
convention. It could be called at physical mode.\r
\r
@param Index Index of PAL_MC_EXPECTED within the list of PAL\r
PAL Procedure - PAL_MC_REGISTER_MEM.\r
\r
Register min-state save area with PAL for machine checks and\r
PAL Procedure - PAL_MC_REGISTER_MEM.\r
\r
Register min-state save area with PAL for machine checks and\r
convention. It could be called at physical and virtual mode.\r
\r
@param Index Index of PAL_HALT_LIGHT within the list of PAL\r
convention. It could be called at physical and virtual mode.\r
\r
@param Index Index of PAL_HALT_LIGHT within the list of PAL\r
Returns alignment and size requirements needed for the memory\r
buffer passed to the PAL_TEST_PROC procedure as well as\r
information on self-test control words for the processor self\r
Returns alignment and size requirements needed for the memory\r
buffer passed to the PAL_TEST_PROC procedure as well as\r
information on self-test control words for the processor self\r
PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode.\r
\r
PAL procedure supports the Static Registers calling\r
convention. It could be called at physical mode.\r
\r
PAL Procedure - PAL_PMI_ENTRYPOINT.\r
\r
Register PMI memory entrypoints with processor. It is required\r
PAL Procedure - PAL_PMI_ENTRYPOINT.\r
\r
Register PMI memory entrypoints with processor. It is required\r
calling convention. It could be called at physical mode.\r
\r
@param Index Index of PAL_PMI_ENTRYPOINT within the list of\r
calling convention. It could be called at physical mode.\r
\r
@param Index Index of PAL_PMI_ENTRYPOINT within the list of\r
convention. It could be called at physical and Virtual mode.\r
\r
@param Index Index of PAL_BRAND_INFO within the list of PAL\r
convention. It could be called at physical and Virtual mode.\r
\r
@param Index Index of PAL_BRAND_INFO within the list of PAL\r
\r
Injects the requested processor error or returns information\r
on the supported injection capabilities for this particular\r
\r
Injects the requested processor error or returns information\r
on the supported injection capabilities for this particular\r
procedure supports the Stacked Registers calling convention.\r
It could be called at physical and Virtual mode.\r
\r
procedure supports the Stacked Registers calling convention.\r
It could be called at physical and Virtual mode.\r
\r
The PAL procedure supports the Stacked Registers calling\r
convention. It could be called at Virtual mode.\r
\r
The PAL procedure supports the Stacked Registers calling\r
convention. It could be called at Virtual mode.\r
\r
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Register a different host IVT and/or a different optional\r
virtualization intercept handler for the virtual processor\r
\r
Register a different host IVT and/or a different optional\r
virtualization intercept handler for the virtual processor\r