+ ## The memory BAR of xhci host controller, in which usb debug feature is enabled.\r
+ ## Note that the memory BAR address is only used before Pci bus resource allocation.\r
+ # @Prompt Configure ehci host controller memory BAR.\r
+ gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbXhciMemorySpaceBase|0xD0000000|UINT64|0x00000007\r
+ \r
+ ## The pci address of xhci host controller, in which usb debug feature is enabled.\r
+ # The format of pci address is :<BR>\r
+ # -----------------------------------------------------------------------<BR>\r
+ # | Bits 28..31 | Bits 20..27 | Bits 15..19 | Bits 12..14 | Bits 00..11 |<BR>\r
+ # -----------------------------------------------------------------------<BR>\r
+ # | 0 | Bus | Device | Function | 0 |<BR>\r
+ # -----------------------------------------------------------------------<BR>\r
+ # For the value 0x000A0000, it means the pci address at bus 0x0, device 0x14, function 0x0.\r
+ # @Prompt Configure xhci host controller pci address.\r
+ # @Expression 0x80000001 | (gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbXhciPciAddress & 0xF0000FFF) == 0\r
+ gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbXhciPciAddress|0x000A0000|UINT32|0x00000008\r
+ \r
+ ## Per XHCI spec, software shall impose a timeout between the detection of the Debug Host \r
+ ## connection and the DbC Run transition to 1. This PCD specifies the timeout value in microsecond.\r
+ # @Prompt Configure debug device detection timeout value.\r
+ gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdUsbXhciDebugDetectTimeout|3000000|UINT64|0x00000009\r
+\r
+[UserExtensions.TianoCore."ExtraFiles"]\r
+ SourceLevelDebugPkgExtra.uni\r