BaseTools/Trim: Normalize filepaths to fix comparisons on Windows

[mirror_edk2.git] / UefiCpuPkg / CpuIo2Dxe / CpuIo2Dxe.c

diff --git a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c
index fd4b2e8524d0db8dcb9cb80e6c9710888f7a9cbd..0f1ca93b2eb1d25e80221b0f9fde16ad7d350ddf 100644 (file)
--- a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c
+++ b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c
@@ -1,14 +1,16 @@
 /** @file\r
   Produces the CPU I/O 2 Protocol.\r
 \r
 /** @file\r
   Produces the CPU I/O 2 Protocol.\r
 \r

-Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials                          \r
-are licensed and made available under the terms and conditions of the BSD License         \r
-which accompanies this distribution.  The full text of the license may be found at        \r
-http://opensource.org/licenses/bsd-license.php                                            \r
-                                                                                          \r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+\r
+This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution.  The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r

 \r
 **/\r
 \r
 \r
 **/\r
 \r


@@ -72,16 +74,16 @@ UINT8 mOutStride[] = {
 /**\r
   Check parameters to a CPU I/O 2 Protocol service request.\r
 \r
 /**\r
   Check parameters to a CPU I/O 2 Protocol service request.\r
 \r

-  The I/O operations are carried out exactly as requested. The caller is responsible \r
-  for satisfying any alignment and I/O width restrictions that a PI System on a \r
-  platform might require. For example on some platforms, width requests of \r
-  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+  The I/O operations are carried out exactly as requested. The caller is responsible\r
+  for satisfying any alignment and I/O width restrictions that a PI System on a\r
+  platform might require. For example on some platforms, width requests of\r
+  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r

   be handled by the driver.\r
   be handled by the driver.\r

-  \r
+\r

   @param[in] MmioOperation  TRUE for an MMIO operation, FALSE for I/O Port operation.\r
   @param[in] Width          Signifies the width of the I/O or Memory operation.\r
   @param[in] MmioOperation  TRUE for an MMIO operation, FALSE for I/O Port operation.\r
   @param[in] Width          Signifies the width of the I/O or Memory operation.\r

-  @param[in] Address        The base address of the I/O operation. \r
-  @param[in] Count          The number of I/O operations to perform. The number of  \r
+  @param[in] Address        The base address of the I/O operation.\r
+  @param[in] Count          The number of I/O operations to perform. The number of\r

                             bytes moved is Width size * Count, starting at Address.\r
   @param[in] Buffer         For read operations, the destination buffer to store the results.\r
                             For write operations, the source buffer from which to write data.\r
                             bytes moved is Width size * Count, starting at Address.\r
   @param[in] Buffer         For read operations, the destination buffer to store the results.\r
                             For write operations, the source buffer from which to write data.\r


@@ -90,7 +92,7 @@ UINT8 mOutStride[] = {
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.\r
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
   @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.\r
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.\r
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
   @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.\r

-  @retval EFI_UNSUPPORTED        The address range specified by Address, Width, \r
+  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,\r

                                  and Count is not valid for this PI system.\r
 \r
 **/\r
                                  and Count is not valid for this PI system.\r
 \r
 **/\r


@@ -116,7 +118,7 @@ CpuIoCheckParameter (
   //\r
   // Check to see if Width is in the valid range\r
   //\r
   //\r
   // Check to see if Width is in the valid range\r
   //\r

-  if (Width < 0 || Width >= EfiCpuIoWidthMaximum) {\r
+  if ((UINT32)Width >= EfiCpuIoWidthMaximum) {\r

     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r


@@ -135,27 +137,27 @@ CpuIoCheckParameter (
   if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
   if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r

-  \r
+\r

   //\r
   // Check to see if Address is aligned\r
   //\r
   //\r
   // Check to see if Address is aligned\r
   //\r

-  if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {\r
+  if ((Address & ((UINT64)mInStride[Width] - 1)) != 0) {\r

     return EFI_UNSUPPORTED;\r
   }\r
 \r
   //\r
     return EFI_UNSUPPORTED;\r
   }\r
 \r
   //\r

-  // Check to see if any address associated with this transfer exceeds the maximum \r
+  // Check to see if any address associated with this transfer exceeds the maximum\r

   // allowed address.  The maximum address implied by the parameters passed in is\r
   // Address + Size * Count.  If the following condition is met, then the transfer\r
   // is not supported.\r
   //\r
   //    Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1\r
   //\r
   // allowed address.  The maximum address implied by the parameters passed in is\r
   // Address + Size * Count.  If the following condition is met, then the transfer\r
   // is not supported.\r
   //\r
   //    Address + Size * Count > (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS) + 1\r
   //\r

-  // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count \r
+  // Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count\r

   // can also be the maximum integer value supported by the CPU, this range\r
   // check must be adjusted to avoid all oveflow conditions.\r
   // can also be the maximum integer value supported by the CPU, this range\r
   // check must be adjusted to avoid all oveflow conditions.\r

-  //   \r
-  // The following form of the range check is equivalent but assumes that \r
+  //\r
+  // The following form of the range check is equivalent but assumes that\r

   // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).\r
   //\r
   Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);\r
   // MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).\r
   //\r
   Limit = (MmioOperation ? MAX_ADDRESS : MAX_IO_PORT_ADDRESS);\r


@@ -163,7 +165,7 @@ CpuIoCheckParameter (
     if (Address > Limit) {\r
       return EFI_UNSUPPORTED;\r
     }\r
     if (Address > Limit) {\r
       return EFI_UNSUPPORTED;\r
     }\r

-  } else {  \r
+  } else {\r

     MaxCount = RShiftU64 (Limit, Width);\r
     if (MaxCount < (Count - 1)) {\r
       return EFI_UNSUPPORTED;\r
     MaxCount = RShiftU64 (Limit, Width);\r
     if (MaxCount < (Count - 1)) {\r
       return EFI_UNSUPPORTED;\r


@@ -175,8 +177,9 @@ CpuIoCheckParameter (
 \r
   //\r
   // Check to see if Buffer is aligned\r
 \r
   //\r
   // Check to see if Buffer is aligned\r

+  // (IA-32 allows UINT64 and INT64 data types to be 32-bit aligned.)\r

   //\r
   //\r

-  if (((UINTN)Buffer & (mInStride[Width] - 1)) != 0) {\r
+  if (((UINTN)Buffer & ((MIN (sizeof (UINTN), mInStride[Width])  - 1))) != 0) {\r

     return EFI_UNSUPPORTED;\r
   }\r
 \r
     return EFI_UNSUPPORTED;\r
   }\r
 \r


@@ -186,30 +189,30 @@ CpuIoCheckParameter (
 /**\r
   Reads memory-mapped registers.\r
 \r
 /**\r
   Reads memory-mapped registers.\r
 \r

-  The I/O operations are carried out exactly as requested. The caller is responsible \r
-  for satisfying any alignment and I/O width restrictions that a PI System on a \r
-  platform might require. For example on some platforms, width requests of \r
-  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+  The I/O operations are carried out exactly as requested. The caller is responsible\r
+  for satisfying any alignment and I/O width restrictions that a PI System on a\r
+  platform might require. For example on some platforms, width requests of\r
+  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r

   be handled by the driver.\r
   be handled by the driver.\r

-  \r
-  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r
-  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r
+\r
+  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
+  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r

   each of the Count operations that is performed.\r
   each of the Count operations that is performed.\r

-  \r
-  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r
-  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r
-  incremented for each of the Count operations that is performed. The read or \r
+\r
+  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
+  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
+  incremented for each of the Count operations that is performed. The read or\r

   write operation is performed Count times on the same Address.\r
   write operation is performed Count times on the same Address.\r

-  \r
-  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r
-  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r
-  incremented for each of the Count operations that is performed. The read or \r
+\r
+  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
+  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
+  incremented for each of the Count operations that is performed. The read or\r

   write operation is performed Count times from the first element of Buffer.\r
   write operation is performed Count times from the first element of Buffer.\r

-  \r
+\r

   @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
   @param[in]  Width    Signifies the width of the I/O or Memory operation.\r
   @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
   @param[in]  Width    Signifies the width of the I/O or Memory operation.\r

-  @param[in]  Address  The base address of the I/O operation. \r
-  @param[in]  Count    The number of I/O operations to perform. The number of \r
+  @param[in]  Address  The base address of the I/O operation.\r
+  @param[in]  Count    The number of I/O operations to perform. The number of\r

                        bytes moved is Width size * Count, starting at Address.\r
   @param[out] Buffer   For read operations, the destination buffer to store the results.\r
                        For write operations, the source buffer from which to write data.\r
                        bytes moved is Width size * Count, starting at Address.\r
   @param[out] Buffer   For read operations, the destination buffer to store the results.\r
                        For write operations, the source buffer from which to write data.\r


@@ -218,7 +221,7 @@ CpuIoCheckParameter (
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.\r
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
   @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.\r
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.\r
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
   @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.\r

-  @retval EFI_UNSUPPORTED        The address range specified by Address, Width, \r
+  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,\r

                                  and Count is not valid for this PI system.\r
 \r
 **/\r
                                  and Count is not valid for this PI system.\r
 \r
 **/\r


@@ -266,30 +269,30 @@ CpuMemoryServiceRead (
 /**\r
   Writes memory-mapped registers.\r
 \r
 /**\r
   Writes memory-mapped registers.\r
 \r

-  The I/O operations are carried out exactly as requested. The caller is responsible \r
-  for satisfying any alignment and I/O width restrictions that a PI System on a \r
-  platform might require. For example on some platforms, width requests of \r
-  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+  The I/O operations are carried out exactly as requested. The caller is responsible\r
+  for satisfying any alignment and I/O width restrictions that a PI System on a\r
+  platform might require. For example on some platforms, width requests of\r
+  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r

   be handled by the driver.\r
   be handled by the driver.\r

-  \r
-  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r
-  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r
+\r
+  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
+  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r

   each of the Count operations that is performed.\r
   each of the Count operations that is performed.\r

-  \r
-  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r
-  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r
-  incremented for each of the Count operations that is performed. The read or \r
+\r
+  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
+  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
+  incremented for each of the Count operations that is performed. The read or\r

   write operation is performed Count times on the same Address.\r
   write operation is performed Count times on the same Address.\r

-  \r
-  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r
-  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r
-  incremented for each of the Count operations that is performed. The read or \r
+\r
+  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
+  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
+  incremented for each of the Count operations that is performed. The read or\r

   write operation is performed Count times from the first element of Buffer.\r
   write operation is performed Count times from the first element of Buffer.\r

-  \r
+\r

   @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
   @param[in]  Width    Signifies the width of the I/O or Memory operation.\r
   @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
   @param[in]  Width    Signifies the width of the I/O or Memory operation.\r

-  @param[in]  Address  The base address of the I/O operation. \r
-  @param[in]  Count    The number of I/O operations to perform. The number of \r
+  @param[in]  Address  The base address of the I/O operation.\r
+  @param[in]  Count    The number of I/O operations to perform. The number of\r

                        bytes moved is Width size * Count, starting at Address.\r
   @param[in]  Buffer   For read operations, the destination buffer to store the results.\r
                        For write operations, the source buffer from which to write data.\r
                        bytes moved is Width size * Count, starting at Address.\r
   @param[in]  Buffer   For read operations, the destination buffer to store the results.\r
                        For write operations, the source buffer from which to write data.\r


@@ -298,7 +301,7 @@ CpuMemoryServiceRead (
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.\r
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
   @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.\r
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.\r
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
   @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.\r

-  @retval EFI_UNSUPPORTED        The address range specified by Address, Width, \r
+  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,\r

                                  and Count is not valid for this PI system.\r
 \r
 **/\r
                                  and Count is not valid for this PI system.\r
 \r
 **/\r


@@ -346,30 +349,30 @@ CpuMemoryServiceWrite (
 /**\r
   Reads I/O registers.\r
 \r
 /**\r
   Reads I/O registers.\r
 \r

-  The I/O operations are carried out exactly as requested. The caller is responsible \r
-  for satisfying any alignment and I/O width restrictions that a PI System on a \r
-  platform might require. For example on some platforms, width requests of \r
-  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+  The I/O operations are carried out exactly as requested. The caller is responsible\r
+  for satisfying any alignment and I/O width restrictions that a PI System on a\r
+  platform might require. For example on some platforms, width requests of\r
+  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r

   be handled by the driver.\r
   be handled by the driver.\r

-  \r
-  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r
-  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r
+\r
+  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
+  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r

   each of the Count operations that is performed.\r
   each of the Count operations that is performed.\r

-  \r
-  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r
-  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r
-  incremented for each of the Count operations that is performed. The read or \r
+\r
+  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
+  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
+  incremented for each of the Count operations that is performed. The read or\r

   write operation is performed Count times on the same Address.\r
   write operation is performed Count times on the same Address.\r

-  \r
-  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r
-  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r
-  incremented for each of the Count operations that is performed. The read or \r
+\r
+  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
+  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
+  incremented for each of the Count operations that is performed. The read or\r

   write operation is performed Count times from the first element of Buffer.\r
   write operation is performed Count times from the first element of Buffer.\r

-  \r
+\r

   @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
   @param[in]  Width    Signifies the width of the I/O or Memory operation.\r
   @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
   @param[in]  Width    Signifies the width of the I/O or Memory operation.\r

-  @param[in]  Address  The base address of the I/O operation. \r
-  @param[in]  Count    The number of I/O operations to perform. The number of \r
+  @param[in]  Address  The base address of the I/O operation.\r
+  @param[in]  Count    The number of I/O operations to perform. The number of\r

                        bytes moved is Width size * Count, starting at Address.\r
   @param[out] Buffer   For read operations, the destination buffer to store the results.\r
                        For write operations, the source buffer from which to write data.\r
                        bytes moved is Width size * Count, starting at Address.\r
   @param[out] Buffer   For read operations, the destination buffer to store the results.\r
                        For write operations, the source buffer from which to write data.\r


@@ -378,7 +381,7 @@ CpuMemoryServiceWrite (
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.\r
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
   @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.\r
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.\r
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
   @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.\r

-  @retval EFI_UNSUPPORTED        The address range specified by Address, Width, \r
+  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,\r

                                  and Count is not valid for this PI system.\r
 \r
 **/\r
                                  and Count is not valid for this PI system.\r
 \r
 **/\r


@@ -409,6 +412,31 @@ CpuIoServiceRead (
   InStride = mInStride[Width];\r
   OutStride = mOutStride[Width];\r
   OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
   InStride = mInStride[Width];\r
   OutStride = mOutStride[Width];\r
   OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r

+\r
+  //\r
+  // Fifo operations supported for (mInStride[Width] == 0)\r
+  //\r
+  if (InStride == 0) {\r
+    switch (OperationWidth) {\r
+    case EfiCpuIoWidthUint8:\r
+      IoReadFifo8 ((UINTN)Address, Count, Buffer);\r
+      return EFI_SUCCESS;\r
+    case EfiCpuIoWidthUint16:\r
+      IoReadFifo16 ((UINTN)Address, Count, Buffer);\r
+      return EFI_SUCCESS;\r
+    case EfiCpuIoWidthUint32:\r
+      IoReadFifo32 ((UINTN)Address, Count, Buffer);\r
+      return EFI_SUCCESS;\r
+    default:\r
+      //\r
+      // The CpuIoCheckParameter call above will ensure that this\r
+      // path is not taken.\r
+      //\r
+      ASSERT (FALSE);\r
+      break;\r
+    }\r
+  }\r
+\r

   for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
     if (OperationWidth == EfiCpuIoWidthUint8) {\r
       *Uint8Buffer = IoRead8 ((UINTN)Address);\r
   for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
     if (OperationWidth == EfiCpuIoWidthUint8) {\r
       *Uint8Buffer = IoRead8 ((UINTN)Address);\r


@@ -425,30 +453,30 @@ CpuIoServiceRead (
 /**\r
   Write I/O registers.\r
 \r
 /**\r
   Write I/O registers.\r
 \r

-  The I/O operations are carried out exactly as requested. The caller is responsible \r
-  for satisfying any alignment and I/O width restrictions that a PI System on a \r
-  platform might require. For example on some platforms, width requests of \r
-  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will \r
+  The I/O operations are carried out exactly as requested. The caller is responsible\r
+  for satisfying any alignment and I/O width restrictions that a PI System on a\r
+  platform might require. For example on some platforms, width requests of\r
+  EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r

   be handled by the driver.\r
   be handled by the driver.\r

-  \r
-  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, \r
-  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for \r
+\r
+  If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r
+  or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r

   each of the Count operations that is performed.\r
   each of the Count operations that is performed.\r

-  \r
-  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, \r
-  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is \r
-  incremented for each of the Count operations that is performed. The read or \r
+\r
+  If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r
+  EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r
+  incremented for each of the Count operations that is performed. The read or\r

   write operation is performed Count times on the same Address.\r
   write operation is performed Count times on the same Address.\r

-  \r
-  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, \r
-  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is \r
-  incremented for each of the Count operations that is performed. The read or \r
+\r
+  If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r
+  EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r
+  incremented for each of the Count operations that is performed. The read or\r

   write operation is performed Count times from the first element of Buffer.\r
   write operation is performed Count times from the first element of Buffer.\r

-  \r
+\r

   @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
   @param[in]  Width    Signifies the width of the I/O or Memory operation.\r
   @param[in]  This     A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r
   @param[in]  Width    Signifies the width of the I/O or Memory operation.\r

-  @param[in]  Address  The base address of the I/O operation. \r
-  @param[in]  Count    The number of I/O operations to perform. The number of \r
+  @param[in]  Address  The base address of the I/O operation.\r
+  @param[in]  Count    The number of I/O operations to perform. The number of\r

                        bytes moved is Width size * Count, starting at Address.\r
   @param[in]  Buffer   For read operations, the destination buffer to store the results.\r
                        For write operations, the source buffer from which to write data.\r
                        bytes moved is Width size * Count, starting at Address.\r
   @param[in]  Buffer   For read operations, the destination buffer to store the results.\r
                        For write operations, the source buffer from which to write data.\r


@@ -457,9 +485,9 @@ CpuIoServiceRead (
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.\r
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
   @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.\r
   @retval EFI_INVALID_PARAMETER  Width is invalid for this PI system.\r
   @retval EFI_INVALID_PARAMETER  Buffer is NULL.\r
   @retval EFI_UNSUPPORTED        The Buffer is not aligned for the given Width.\r

-  @retval EFI_UNSUPPORTED        The address range specified by Address, Width, \r
+  @retval EFI_UNSUPPORTED        The address range specified by Address, Width,\r

                                  and Count is not valid for this PI system.\r
                                  and Count is not valid for this PI system.\r

-                                 \r
+\r

 **/\r
 EFI_STATUS\r
 EFIAPI\r
 **/\r
 EFI_STATUS\r
 EFIAPI\r


@@ -491,6 +519,31 @@ CpuIoServiceWrite (
   InStride = mInStride[Width];\r
   OutStride = mOutStride[Width];\r
   OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
   InStride = mInStride[Width];\r
   OutStride = mOutStride[Width];\r
   OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r

+\r
+  //\r
+  // Fifo operations supported for (mInStride[Width] == 0)\r
+  //\r
+  if (InStride == 0) {\r
+    switch (OperationWidth) {\r
+    case EfiCpuIoWidthUint8:\r
+      IoWriteFifo8 ((UINTN)Address, Count, Buffer);\r
+      return EFI_SUCCESS;\r
+    case EfiCpuIoWidthUint16:\r
+      IoWriteFifo16 ((UINTN)Address, Count, Buffer);\r
+      return EFI_SUCCESS;\r
+    case EfiCpuIoWidthUint32:\r
+      IoWriteFifo32 ((UINTN)Address, Count, Buffer);\r
+      return EFI_SUCCESS;\r
+    default:\r
+      //\r
+      // The CpuIoCheckParameter call above will ensure that this\r
+      // path is not taken.\r
+      //\r
+      ASSERT (FALSE);\r
+      break;\r
+    }\r
+  }\r
+\r

   for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
     if (OperationWidth == EfiCpuIoWidthUint8) {\r
       IoWrite8 ((UINTN)Address, *Uint8Buffer);\r
   for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
     if (OperationWidth == EfiCpuIoWidthUint8) {\r
       IoWrite8 ((UINTN)Address, *Uint8Buffer);\r


@@ -500,16 +553,16 @@ CpuIoServiceWrite (
       IoWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));\r
     }\r
   }\r
       IoWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));\r
     }\r
   }\r

-  \r
+\r

   return EFI_SUCCESS;\r
 }\r
 \r
 /**\r
   The user Entry Point for module CpuIo2Dxe. The user code starts with this function.\r
 \r
   return EFI_SUCCESS;\r
 }\r
 \r
 /**\r
   The user Entry Point for module CpuIo2Dxe. The user code starts with this function.\r
 \r

-  @param[in] ImageHandle    The firmware allocated handle for the EFI image.  \r
+  @param[in] ImageHandle    The firmware allocated handle for the EFI image.\r

   @param[in] SystemTable    A pointer to the EFI System Table.\r
   @param[in] SystemTable    A pointer to the EFI System Table.\r

-  \r
+\r

   @retval EFI_SUCCESS       The entry point is executed successfully.\r
   @retval other             Some error occurs when executing this entry point.\r
 \r
   @retval EFI_SUCCESS       The entry point is executed successfully.\r
   @retval other             Some error occurs when executing this entry point.\r
 \r