-/**\r
- Shared. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_ATOM_MC3_CTL (0x0000040C)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_MC3_CTL);\r
- AsmWriteMsr64 (MSR_ATOM_MC3_CTL, Msr);\r
- @endcode\r
- @note MSR_ATOM_MC3_CTL is defined as MSR_MC3_CTL in SDM.\r
-**/\r
-#define MSR_ATOM_MC3_CTL 0x0000040C\r
-\r
-\r
-/**\r
- Shared. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_ATOM_MC3_STATUS (0x0000040D)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_MC3_STATUS);\r
- AsmWriteMsr64 (MSR_ATOM_MC3_STATUS, Msr);\r
- @endcode\r
- @note MSR_ATOM_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.\r
-**/\r
-#define MSR_ATOM_MC3_STATUS 0x0000040D\r
-\r
-\r
-/**\r
- Shared. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR\r
- register is either not implemented or contains no address if the ADDRV flag\r
- in the MSR_MC3_STATUS register is clear. When not implemented in the\r
- processor, all reads and writes to this MSR will cause a general-protection\r
- exception.\r
-\r
- @param ECX MSR_ATOM_MC3_ADDR (0x0000040E)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_MC3_ADDR);\r
- AsmWriteMsr64 (MSR_ATOM_MC3_ADDR, Msr);\r
- @endcode\r
- @note MSR_ATOM_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
-**/\r
-#define MSR_ATOM_MC3_ADDR 0x0000040E\r
-\r
-\r
-/**\r
- Shared. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
-\r
- @param ECX MSR_ATOM_MC4_CTL (0x00000410)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_MC4_CTL);\r
- AsmWriteMsr64 (MSR_ATOM_MC4_CTL, Msr);\r
- @endcode\r
- @note MSR_ATOM_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
-**/\r
-#define MSR_ATOM_MC4_CTL 0x00000410\r
-\r
-\r
-/**\r
- Shared. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
-\r
- @param ECX MSR_ATOM_MC4_STATUS (0x00000411)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_MC4_STATUS);\r
- AsmWriteMsr64 (MSR_ATOM_MC4_STATUS, Msr);\r
- @endcode\r
- @note MSR_ATOM_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
-**/\r
-#define MSR_ATOM_MC4_STATUS 0x00000411\r
-\r
-\r
-/**\r
- Shared. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR\r
- register is either not implemented or contains no address if the ADDRV flag\r
- in the MSR_MC4_STATUS register is clear. When not implemented in the\r
- processor, all reads and writes to this MSR will cause a general-protection\r
- exception.\r
-\r
- @param ECX MSR_ATOM_MC4_ADDR (0x00000412)\r
- @param EAX Lower 32-bits of MSR value.\r
- @param EDX Upper 32-bits of MSR value.\r
-\r
- <b>Example usage</b>\r
- @code\r
- UINT64 Msr;\r
-\r
- Msr = AsmReadMsr64 (MSR_ATOM_MC4_ADDR);\r
- AsmWriteMsr64 (MSR_ATOM_MC4_ADDR, Msr);\r
- @endcode\r
- @note MSR_ATOM_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
-**/\r
-#define MSR_ATOM_MC4_ADDR 0x00000412\r
-\r
-\r