2 MSR Definitions for the Intel(R) Atom(TM) Processor Family.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.3.
24 #ifndef __ATOM_MSR_H__
25 #define __ATOM_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Shared. Model Specific Platform ID (R).
32 @param ECX MSR_ATOM_PLATFORM_ID (0x00000017)
33 @param EAX Lower 32-bits of MSR value.
34 Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
35 @param EDX Upper 32-bits of MSR value.
36 Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.
40 MSR_ATOM_PLATFORM_ID_REGISTER Msr;
42 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);
44 @note MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.
46 #define MSR_ATOM_PLATFORM_ID 0x00000017
49 MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID
53 /// Individual bit fields
58 /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.
60 UINT32 MaximumQualifiedRatio
:5;
65 /// All bit fields as a 32-bit value
69 /// All bit fields as a 64-bit value
72 } MSR_ATOM_PLATFORM_ID_REGISTER
;
76 Shared. Processor Hard Power-On Configuration (R/W) Enables and disables
77 processor features; (R) indicates current processor configuration.
79 @param ECX MSR_ATOM_EBL_CR_POWERON (0x0000002A)
80 @param EAX Lower 32-bits of MSR value.
81 Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
82 @param EDX Upper 32-bits of MSR value.
83 Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.
87 MSR_ATOM_EBL_CR_POWERON_REGISTER Msr;
89 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);
90 AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);
92 @note MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.
94 #define MSR_ATOM_EBL_CR_POWERON 0x0000002A
97 MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON
101 /// Individual bit fields
106 /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
109 UINT32 DataErrorCheckingEnable
:1;
111 /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled
114 UINT32 ResponseErrorCheckingEnable
:1;
116 /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
118 UINT32 AERR_DriveEnable
:1;
120 /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =
121 /// Disabled Always 0.
123 UINT32 BERR_Enable
:1;
127 /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.
129 UINT32 BINIT_DriverEnable
:1;
132 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.
134 UINT32 ExecuteBIST
:1;
136 /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
139 UINT32 AERR_ObservationEnabled
:1;
142 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled
145 UINT32 BINIT_ObservationEnabled
:1;
148 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.
150 UINT32 ResetVector
:1;
153 /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.
155 UINT32 APICClusterID
:2;
158 /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.
160 UINT32 SymmetricArbitrationID
:2;
162 /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).
164 UINT32 IntegerBusFrequencyRatio
:5;
166 UINT32 Reserved10
:32;
169 /// All bit fields as a 32-bit value
173 /// All bit fields as a 64-bit value
176 } MSR_ATOM_EBL_CR_POWERON_REGISTER
;
180 Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch
181 record registers on the last branch record stack. The From_IP part of the
182 stack contains pointers to the source instruction . See also: - Last Branch
183 Record Stack TOS at 1C9H - Section 17.5.
185 @param ECX MSR_ATOM_LASTBRANCH_n_FROM_IP
186 @param EAX Lower 32-bits of MSR value.
187 @param EDX Upper 32-bits of MSR value.
193 Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);
194 AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);
196 @note MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.
197 MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.
198 MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.
199 MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.
200 MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.
201 MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.
202 MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.
203 MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.
206 #define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040
207 #define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041
208 #define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042
209 #define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043
210 #define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044
211 #define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045
212 #define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046
213 #define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047
218 Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch
219 record registers on the last branch record stack. The To_IP part of the
220 stack contains pointers to the destination instruction.
222 @param ECX MSR_ATOM_LASTBRANCH_n_TO_IP
223 @param EAX Lower 32-bits of MSR value.
224 @param EDX Upper 32-bits of MSR value.
230 Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);
231 AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);
233 @note MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.
234 MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.
235 MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.
236 MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.
237 MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.
238 MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.
239 MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.
240 MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.
243 #define MSR_ATOM_LASTBRANCH_0_TO_IP 0x00000060
244 #define MSR_ATOM_LASTBRANCH_1_TO_IP 0x00000061
245 #define MSR_ATOM_LASTBRANCH_2_TO_IP 0x00000062
246 #define MSR_ATOM_LASTBRANCH_3_TO_IP 0x00000063
247 #define MSR_ATOM_LASTBRANCH_4_TO_IP 0x00000064
248 #define MSR_ATOM_LASTBRANCH_5_TO_IP 0x00000065
249 #define MSR_ATOM_LASTBRANCH_6_TO_IP 0x00000066
250 #define MSR_ATOM_LASTBRANCH_7_TO_IP 0x00000067
255 Shared. Scalable Bus Speed(RO) This field indicates the intended scalable
256 bus clock speed for processors based on Intel Atom microarchitecture:.
258 @param ECX MSR_ATOM_FSB_FREQ (0x000000CD)
259 @param EAX Lower 32-bits of MSR value.
260 Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
261 @param EDX Upper 32-bits of MSR value.
262 Described by the type MSR_ATOM_FSB_FREQ_REGISTER.
266 MSR_ATOM_FSB_FREQ_REGISTER Msr;
268 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ);
270 @note MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.
272 #define MSR_ATOM_FSB_FREQ 0x000000CD
275 MSR information returned for MSR index #MSR_ATOM_FSB_FREQ
279 /// Individual bit fields
283 /// [Bits 2:0] - Scalable Bus Speed
285 /// Atom Processor Family
286 /// ---------------------
287 /// 111B: 083 MHz (FSB 333)
288 /// 101B: 100 MHz (FSB 400)
289 /// 001B: 133 MHz (FSB 533)
290 /// 011B: 167 MHz (FSB 667)
292 /// 133.33 MHz should be utilized if performing calculation with
293 /// System Bus Speed when encoding is 001B.
294 /// 166.67 MHz should be utilized if performing calculation with
295 /// System Bus Speed when
296 /// encoding is 011B.
298 UINT32 ScalableBusSpeed
:3;
303 /// All bit fields as a 32-bit value
307 /// All bit fields as a 64-bit value
310 } MSR_ATOM_FSB_FREQ_REGISTER
;
316 @param ECX MSR_ATOM_BBL_CR_CTL3 (0x0000011E)
317 @param EAX Lower 32-bits of MSR value.
318 Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
319 @param EDX Upper 32-bits of MSR value.
320 Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.
324 MSR_ATOM_BBL_CR_CTL3_REGISTER Msr;
326 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3);
327 AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64);
329 @note MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.
331 #define MSR_ATOM_BBL_CR_CTL3 0x0000011E
334 MSR information returned for MSR index #MSR_ATOM_BBL_CR_CTL3
338 /// Individual bit fields
342 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =
343 /// Indicates if the L2 is hardware-disabled.
345 UINT32 L2HardwareEnabled
:1;
348 /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =
349 /// Disabled (default) Until this bit is set the processor will not
350 /// respond to the WBINVD instruction or the assertion of the FLUSH# input.
355 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.
357 UINT32 L2NotPresent
:1;
362 /// All bit fields as a 32-bit value
366 /// All bit fields as a 64-bit value
369 } MSR_ATOM_BBL_CR_CTL3_REGISTER
;
375 @param ECX MSR_ATOM_PERF_STATUS (0x00000198)
376 @param EAX Lower 32-bits of MSR value.
377 Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
378 @param EDX Upper 32-bits of MSR value.
379 Described by the type MSR_ATOM_PERF_STATUS_REGISTER.
383 MSR_ATOM_PERF_STATUS_REGISTER Msr;
385 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS);
386 AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64);
388 @note MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.
390 #define MSR_ATOM_PERF_STATUS 0x00000198
393 MSR information returned for MSR index #MSR_ATOM_PERF_STATUS
397 /// Individual bit fields
401 /// [Bits 15:0] Current Performance State Value.
403 UINT32 CurrentPerformanceStateValue
:16;
407 /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio
408 /// configured for the processor.
410 UINT32 MaximumBusRatio
:5;
414 /// All bit fields as a 64-bit value
417 } MSR_ATOM_PERF_STATUS_REGISTER
;
423 @param ECX MSR_ATOM_THERM2_CTL (0x0000019D)
424 @param EAX Lower 32-bits of MSR value.
425 Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
426 @param EDX Upper 32-bits of MSR value.
427 Described by the type MSR_ATOM_THERM2_CTL_REGISTER.
431 MSR_ATOM_THERM2_CTL_REGISTER Msr;
433 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL);
434 AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64);
436 @note MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.
438 #define MSR_ATOM_THERM2_CTL 0x0000019D
441 MSR information returned for MSR index #MSR_ATOM_THERM2_CTL
445 /// Individual bit fields
450 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =
451 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the
452 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated
453 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is
454 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.
461 /// All bit fields as a 32-bit value
465 /// All bit fields as a 64-bit value
468 } MSR_ATOM_THERM2_CTL_REGISTER
;
472 Unique. Enable Misc. Processor Features (R/W) Allows a variety of processor
473 functions to be enabled and disabled.
475 @param ECX MSR_ATOM_IA32_MISC_ENABLE (0x000001A0)
476 @param EAX Lower 32-bits of MSR value.
477 Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
478 @param EDX Upper 32-bits of MSR value.
479 Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.
483 MSR_ATOM_IA32_MISC_ENABLE_REGISTER Msr;
485 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE);
486 AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64);
488 @note MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
490 #define MSR_ATOM_IA32_MISC_ENABLE 0x000001A0
493 MSR information returned for MSR index #MSR_ATOM_IA32_MISC_ENABLE
497 /// Individual bit fields
501 /// [Bit 0] Fast-Strings Enable See Table 35-2.
503 UINT32 FastStrings
:1;
506 /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See
507 /// Table 35-2. Default value is 0.
509 UINT32 AutomaticThermalControlCircuit
:1;
512 /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.
514 UINT32 PerformanceMonitoring
:1;
518 /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by
519 /// the processor to indicate a pending break event within the processor 0
520 /// = Indicates compatible FERR# signaling behavior This bit must be set
521 /// to 1 to support XAPIC interrupt model usage.
525 /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.
529 /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See
534 /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the
535 /// thermal sensor indicates that the die temperature is at the
536 /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.
537 /// TM2 will reduce the bus to core ratio and voltage according to the
538 /// value last written to MSR_THERM2_CTL bits 15:0.
539 /// When this bit is clear (0, default), the processor does not change
540 /// the VID signals or the bus to core ratio when the processor enters a
541 /// thermally managed state. The BIOS must enable this feature if the
542 /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is
543 /// not set, this feature is not supported and BIOS must not alter the
544 /// contents of the TM2 bit location. The processor is operating out of
545 /// specification if both this bit and the TM1 bit are set to 0.
550 /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See
556 /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.
561 /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock
562 /// (R/WO) When set, this bit causes the following bits to become
563 /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this
564 /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must
565 /// be set before an Enhanced Intel SpeedStep Technology transition is
566 /// requested. This bit is cleared on reset.
571 /// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 35-2.
573 UINT32 LimitCpuidMaxval
:1;
575 /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.
577 UINT32 xTPR_Message_Disable
:1;
581 /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.
584 UINT32 Reserved11
:29;
587 /// All bit fields as a 64-bit value
590 } MSR_ATOM_IA32_MISC_ENABLE_REGISTER
;
594 Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2)
595 that points to the MSR containing the most recent branch record. See
596 MSR_LASTBRANCH_0_FROM_IP (at 40H).
598 @param ECX MSR_ATOM_LASTBRANCH_TOS (0x000001C9)
599 @param EAX Lower 32-bits of MSR value.
600 @param EDX Upper 32-bits of MSR value.
606 Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS);
607 AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr);
609 @note MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.
611 #define MSR_ATOM_LASTBRANCH_TOS 0x000001C9
615 Unique. Last Exception Record From Linear IP (R) Contains a pointer to the
616 last branch instruction that the processor executed prior to the last
617 exception that was generated or the last interrupt that was handled.
619 @param ECX MSR_ATOM_LER_FROM_LIP (0x000001DD)
620 @param EAX Lower 32-bits of MSR value.
621 @param EDX Upper 32-bits of MSR value.
627 Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP);
629 @note MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.
631 #define MSR_ATOM_LER_FROM_LIP 0x000001DD
635 Unique. Last Exception Record To Linear IP (R) This area contains a pointer
636 to the target of the last branch instruction that the processor executed
637 prior to the last exception that was generated or the last interrupt that
640 @param ECX MSR_ATOM_LER_TO_LIP (0x000001DE)
641 @param EAX Lower 32-bits of MSR value.
642 @param EDX Upper 32-bits of MSR value.
648 Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP);
650 @note MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.
652 #define MSR_ATOM_LER_TO_LIP 0x000001DE
656 Unique. See Table 35-2. See Section 18.4.4, "Processor Event Based Sampling
659 @param ECX MSR_ATOM_PEBS_ENABLE (0x000003F1)
660 @param EAX Lower 32-bits of MSR value.
661 Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
662 @param EDX Upper 32-bits of MSR value.
663 Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.
667 MSR_ATOM_PEBS_ENABLE_REGISTER Msr;
669 Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PEBS_ENABLE);
670 AsmWriteMsr64 (MSR_ATOM_PEBS_ENABLE, Msr.Uint64);
672 @note MSR_ATOM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.
674 #define MSR_ATOM_PEBS_ENABLE 0x000003F1
677 MSR information returned for MSR index #MSR_ATOM_PEBS_ENABLE
681 /// Individual bit fields
685 /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).
692 /// All bit fields as a 32-bit value
696 /// All bit fields as a 64-bit value
699 } MSR_ATOM_PEBS_ENABLE_REGISTER
;
703 Package. Package C2 Residency Note: C-state values are processor specific
704 C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
705 C-States. Package. Package C2 Residency Counter. (R/O) Time that this
706 package is in processor-specific C2 states since last reset. Counts at 1 Mhz
709 @param ECX MSR_ATOM_PKG_C2_RESIDENCY (0x000003F8)
710 @param EAX Lower 32-bits of MSR value.
711 @param EDX Upper 32-bits of MSR value.
717 Msr = AsmReadMsr64 (MSR_ATOM_PKG_C2_RESIDENCY);
718 AsmWriteMsr64 (MSR_ATOM_PKG_C2_RESIDENCY, Msr);
720 @note MSR_ATOM_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.
722 #define MSR_ATOM_PKG_C2_RESIDENCY 0x000003F8
726 Package. Package C4 Residency Note: C-state values are processor specific
727 C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
728 C-States. Package. Package C4 Residency Counter. (R/O) Time that this
729 package is in processor-specific C4 states since last reset. Counts at 1 Mhz
732 @param ECX MSR_ATOM_PKG_C4_RESIDENCY (0x000003F9)
733 @param EAX Lower 32-bits of MSR value.
734 @param EDX Upper 32-bits of MSR value.
740 Msr = AsmReadMsr64 (MSR_ATOM_PKG_C4_RESIDENCY);
741 AsmWriteMsr64 (MSR_ATOM_PKG_C4_RESIDENCY, Msr);
743 @note MSR_ATOM_PKG_C4_RESIDENCY is defined as MSR_PKG_C4_RESIDENCY in SDM.
745 #define MSR_ATOM_PKG_C4_RESIDENCY 0x000003F9
749 Package. Package C6 Residency Note: C-state values are processor specific
750 C-state code names, unrelated to MWAIT extension C-state parameters or ACPI
751 C-States. Package. Package C6 Residency Counter. (R/O) Time that this
752 package is in processor-specific C6 states since last reset. Counts at 1 Mhz
755 @param ECX MSR_ATOM_PKG_C6_RESIDENCY (0x000003FA)
756 @param EAX Lower 32-bits of MSR value.
757 @param EDX Upper 32-bits of MSR value.
763 Msr = AsmReadMsr64 (MSR_ATOM_PKG_C6_RESIDENCY);
764 AsmWriteMsr64 (MSR_ATOM_PKG_C6_RESIDENCY, Msr);
766 @note MSR_ATOM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.
768 #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003FA