# ARM processor package.\r
#\r
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011 - 2015, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011 - 2017, ARM Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
\r
[LibraryClasses.common]\r
ArmLib|Include/Library/ArmLib.h\r
+ ArmMmuLib|Include/Library/ArmMmuLib.h\r
SemihostLib|Include/Library/Semihosting.h\r
UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h\r
DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h\r
gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C\r
gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E\r
\r
+ #\r
+ # Value to add to a host address to obtain a device address, using\r
+ # unsigned 64-bit integer arithmetic on both ARM and AArch64. This\r
+ # means we can rely on truncation on overflow to specify negative\r
+ # offsets.\r
+ #\r
+ gArmTokenSpaceGuid.PcdArmDmaDeviceOffset|0x0|UINT64|0x0000044\r
+\r
[PcdsFixedAtBuild.common, PcdsPatchableInModule.common]\r
gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B\r
gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D\r
# ARM Generic Watchdog\r
#\r
\r
- gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT32|0x00000007\r
- gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT32|0x00000008\r
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT64|0x00000007\r
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT64|0x00000008\r
gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009\r
\r
#\r
# ARM Generic Interrupt Controller\r
#\r
- gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C\r
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT64|0x0000000C\r
# Base address for the GIC Redistributor region that contains the boot CPU\r
- gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT32|0x0000000E\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D\r
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT64|0x0000000E\r
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT64|0x0000000D\r
gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025\r
+\r
+ #\r
+ # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.\r
+ # Note that "IO" is just another MMIO range that simulates IO space; there\r
+ # are no special instructions to access it.\r
+ #\r
+ # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are\r
+ # specific to their containing address spaces. In order to get the physical\r
+ # address for the CPU, for a given access, the respective translation value\r
+ # has to be added.\r
+ #\r
+ # The translations always have to be initialized like this, using UINT64:\r
+ #\r
+ # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space\r
+ # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space\r
+ # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space\r
+ #\r
+ # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;\r
+ # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;\r
+ # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;\r
+ #\r
+ # because (a) the target address space (ie. the cpu-physical space) is\r
+ # 64-bit, and (b) the translation values are meant as offsets for *modular*\r
+ # arithmetic.\r
+ #\r
+ # Accordingly, the translation itself needs to be implemented as:\r
+ #\r
+ # UINT64 UntranslatedIoAddress; // input parameter\r
+ # UINT32 UntranslatedMmio32Address; // input parameter\r
+ # UINT64 UntranslatedMmio64Address; // input parameter\r
+ #\r
+ # UINT64 TranslatedIoAddress; // output parameter\r
+ # UINT64 TranslatedMmio32Address; // output parameter\r
+ # UINT64 TranslatedMmio64Address; // output parameter\r
+ #\r
+ # TranslatedIoAddress = UntranslatedIoAddress +\r
+ # PcdPciIoTranslation;\r
+ # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +\r
+ # PcdPciMmio32Translation;\r
+ # TranslatedMmio64Address = UntranslatedMmio64Address +\r
+ # PcdPciMmio64Translation;\r
+ #\r
+ # The modular arithmetic performed in UINT64 ensures that the translation\r
+ # works correctly regardless of the relation between IoCpuBase and\r
+ # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and\r
+ # PcdPciMmio64Base.\r
+ #\r
+ gArmTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000050\r
+ gArmTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000051\r
+ gArmTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000052\r
+ gArmTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000053\r
+ gArmTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000054\r
+ gArmTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000055\r
+ gArmTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000056\r
+ gArmTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000057\r
+ gArmTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000058\r
+\r
+ #\r
+ # Inclusive range of allowed PCI buses.\r
+ #\r
+ gArmTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x00000059\r
+ gArmTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000005A\r