ArmPkg/ArmGic: enable ARE bit before driving GICv3 in native mode

[mirror_edk2.git] / ArmPkg / Drivers / ArmGic / ArmGicLib.c

diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
index 7c53e39793df7f9c1c2368c587bb6e16cc1e55a6..48708e3812b4736fcd2399e05a92cab02f532555 100644 (file)
--- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
+++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
@@ -186,7 +186,7 @@ ArmGicEnableInterrupt (
   RegShift = Source % 32;\r
 \r
   Revision = ArmGicGetSupportedArchRevision ();\r
-  if (Revision == ARM_GIC_ARCH_REVISION_2) {\r
+  if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {\r
     // Write set-enable register\r
     MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset), 1 << RegShift);\r
   } else {\r
@@ -219,7 +219,7 @@ ArmGicDisableInterrupt (
   RegShift = Source % 32;\r
 \r
   Revision = ArmGicGetSupportedArchRevision ();\r
-  if (Revision == ARM_GIC_ARCH_REVISION_2) {\r
+  if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {\r
     // Write clear-enable register\r
     MmioWrite32 (GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset), 1 << RegShift);\r
   } else {\r
@@ -252,7 +252,7 @@ ArmGicIsInterruptEnabled (
   RegShift = Source % 32;\r
 \r
   Revision = ArmGicGetSupportedArchRevision ();\r
-  if (Revision == ARM_GIC_ARCH_REVISION_2) {\r
+  if ((Revision == ARM_GIC_ARCH_REVISION_2) || FeaturePcdGet (PcdArmGicV3WithV2Legacy)) {\r
     Interrupts = ((MmioRead32 (GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)) & (1 << RegShift)) != 0);\r
   } else {\r
     GicCpuRedistributorBase = GicGetCpuRedistributorBase (GicRedistributorBase, Revision);\r