ArmPkg: Fix various typos

[mirror_edk2.git] / ArmPkg / Drivers / CpuDxe / CpuDxe.c

diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/ArmPkg/Drivers/CpuDxe/CpuDxe.c
index 0c49acb510831eb5a4e9bc43f767e091c612ed12..082ef30fb6c40b063f48523839087a3f5dcb2bae 100644 (file)
--- a/ArmPkg/Drivers/CpuDxe/CpuDxe.c
+++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.c
@@ -3,13 +3,7 @@
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
   Copyright (c) 2011, ARM Limited. All rights reserved.\r
 \r
-  This program and the accompanying materials\r
-  are licensed and made available under the terms and conditions of the BSD License\r
-  which accompanies this distribution.  The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php\r
-\r
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
 \r
@@ -17,8 +11,7 @@
 \r
 #include <Guid/IdleLoopEvent.h>\r
 \r
-BOOLEAN mInterruptState   = FALSE;\r
-\r
+BOOLEAN                   mIsFlushingGCD;\r
 \r
 /**\r
   This function flushes the range of addresses from Start to Start+Length\r
@@ -41,7 +34,7 @@ BOOLEAN mInterruptState   = FALSE;
 \r
   @retval EFI_SUCCESS           The address range from Start to Start+Length was flushed from\r
                                 the processor's data cache.\r
-  @retval EFI_UNSUPPORTEDT      The processor does not support the cache flush type specified\r
+  @retval EFI_UNSUPPORTED       The processor does not support the cache flush type specified\r
                                 by FlushType.\r
   @retval EFI_DEVICE_ERROR      The address range from Start to Start+Length could not be flushed\r
                                 from the processor's data cache.\r
@@ -92,7 +85,6 @@ CpuEnableInterrupt (
 {\r
   ArmEnableInterrupts ();\r
 \r
-  mInterruptState  = TRUE;\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -114,7 +106,6 @@ CpuDisableInterrupt (
 {\r
   ArmDisableInterrupts ();\r
 \r
-  mInterruptState = FALSE;\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -143,7 +134,7 @@ CpuGetInterruptState (
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
-  *State = mInterruptState;\r
+  *State = ArmGetInterruptState();\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -229,9 +220,18 @@ EFI_CPU_ARCH_PROTOCOL mCpu = {
   CpuGetTimerValue,\r
   CpuSetMemoryAttributes,\r
   0,          // NumberOfTimers\r
-  4,          // DmaBufferAlignment\r
+  2048,       // DmaBufferAlignment\r
 };\r
 \r
+STATIC\r
+VOID\r
+InitializeDma (\r
+  IN OUT  EFI_CPU_ARCH_PROTOCOL   *CpuArchProtocol\r
+  )\r
+{\r
+  CpuArchProtocol->DmaBufferAlignment = ArmCacheWritebackGranule ();\r
+}\r
+\r
 EFI_STATUS\r
 CpuDxeInitialize (\r
   IN EFI_HANDLE         ImageHandle,\r
@@ -243,10 +243,11 @@ CpuDxeInitialize (
 \r
   InitializeExceptions (&mCpu);\r
 \r
+  InitializeDma (&mCpu);\r
+\r
   Status = gBS->InstallMultipleProtocolInterfaces (\r
                 &mCpuHandle,\r
                 &gEfiCpuArchProtocolGuid,           &mCpu,\r
-                &gVirtualUncachedPagesProtocolGuid, &gVirtualUncachedPages,\r
                 NULL\r
                 );\r
 \r
@@ -255,7 +256,9 @@ CpuDxeInitialize (
   // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go\r
   // after the protocol is installed\r
   //\r
+  mIsFlushingGCD = TRUE;\r
   SyncCacheConfig (&mCpu);\r
+  mIsFlushingGCD = FALSE;\r
 \r
   // If the platform is a MPCore system then install the Configuration Table describing the\r
   // secondary core states\r