Fix various typos in ArmPkg.
Signed-off-by: Coeur <coeur@gmx.fr>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
//\r
// Since MAX_ADDRESS can be the maximum integer value supported by the CPU and Count\r
// can also be the maximum integer value supported by the CPU, this range\r
- // check must be adjusted to avoid all oveflow conditions.\r
+ // check must be adjusted to avoid all overflow conditions.\r
//\r
// The following form of the range check is equivalent but assumes that\r
// MAX_ADDRESS and MAX_IO_PORT_ADDRESS are of the form (2^n - 1).\r
BlockEntry++;\r
} else if (EntryType == BlockEntryType) {\r
// We have found the BlockEntry attached to the address. We save its start address (the start\r
- // address might be before the 'BaseAdress') and attributes\r
+ // address might be before the 'BaseAddress') and attributes\r
*BaseAddress = *BaseAddress & ~(TT_ADDRESS_AT_LEVEL(TableLevel) - 1);\r
*RegionLength = 0;\r
*RegionAttributes = *BlockEntry & TT_ATTRIBUTES_MASK;\r
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;\r
\r
\r
- DEBUG ((EFI_D_PAGE, "SyncCacheConfig()\n"));\r
+ DEBUG ((DEBUG_PAGE, "SyncCacheConfig()\n"));\r
\r
// This code assumes MMU is enabled and filed with section translations\r
ASSERT (ArmMmuEnabled ());\r
\r
if ((BaseAddress & (SIZE_4KB - 1)) != 0) {\r
// Minimum granularity is SIZE_4KB (4KB on ARM)\r
- DEBUG ((EFI_D_PAGE, "CpuSetMemoryAttributes(%lx, %lx, %lx): Minimum ganularity is SIZE_4KB\n", BaseAddress, Length, EfiAttributes));\r
+ DEBUG ((DEBUG_PAGE, "CpuSetMemoryAttributes(%lx, %lx, %lx): Minimum granularity is SIZE_4KB\n", BaseAddress, Length, EfiAttributes));\r
return EFI_UNSUPPORTED;\r
}\r
\r
// Allocate Runtime memory for ARM processor table\r
ArmProcessorTable = (ARM_PROCESSOR_TABLE*)AllocateRuntimePool(sizeof(ARM_PROCESSOR_TABLE));\r
\r
- // Check if the memory allocation is succesful or not\r
+ // Check if the memory allocation is successful or not\r
ASSERT(NULL != ArmProcessorTable);\r
\r
// Set ARM processor table to default values\r
ArmProcessorTable->ArmCpus = (ARM_CORE_INFO*)AllocateRuntimePool (\r
ArmProcessorTable->NumberOfEntries * sizeof(ARM_CORE_INFO));\r
\r
- // Check if the memory allocation is succesful or not\r
+ // Check if the memory allocation is successful or not\r
ASSERT(NULL != ArmProcessorTable->ArmCpus);\r
\r
// Copy ARM Processor Table data from HOB list to newly allocated memory\r
VectorInfo = VectorInfoList;\r
}\r
\r
- // intialize the CpuExceptionHandlerLib so we take over the exception vector table from the DXE Core\r
+ // initialize the CpuExceptionHandlerLib so we take over the exception vector table from the DXE Core\r
InitializeCpuExceptionHandlers(VectorInfo);\r
\r
Status = EFI_SUCCESS;\r
//\r
#include <PiPei.h>\r
//\r
-// The protocols, PPI and GUID defintions for this module\r
+// The protocols, PPI and GUID definitions for this module\r
//\r
#include <Ppi/ArmMpCoreInfo.h>\r
\r
UINT32 TimerHypIntrNum;\r
\r
if (ArmIsArchTimerImplemented () == 0) {\r
- DEBUG ((EFI_D_ERROR, "ARM Architectural Timer is not available in the CPU, hence cann't use this Driver \n"));\r
+ DEBUG ((DEBUG_ERROR, "ARM Architectural Timer is not available in the CPU, hence can't use this Driver \n"));\r
ASSERT (0);\r
}\r
\r
@param[in] Position The byte position from the start of the file to set.\r
\r
@retval EFI_SUCCESS The position was set.\r
- @retval EFI_DEVICE_ERROR The semi-hosting positionning operation failed.\r
+ @retval EFI_DEVICE_ERROR The semi-hosting positioning operation failed.\r
@retval EFI_UNSUPPORTED The seek request for nonzero is not valid on open\r
directories.\r
@retval EFI_INVALID_PARAMETER The parameter "This" is NULL.\r
@param[in] Position The byte position from the start of the file to set.\r
\r
@retval EFI_SUCCESS The position was set.\r
- @retval EFI_DEVICE_ERROR The semi-hosting positionning operation failed.\r
+ @retval EFI_DEVICE_ERROR The semi-hosting positioning operation failed.\r
@retval EFI_UNSUPPORTED The seek request for nonzero is not valid on open\r
directories.\r
\r
#define __ARM_DISASSEBLER_LIB_H__\r
\r
/**\r
- Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to\r
- point to next instructin.\r
+ Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to\r
+ point to next instruction.\r
\r
We cheat and only decode instructions that access\r
memory. If the instruction is not found we dump the instruction in hex.\r
\r
@param NanoSeconds The minimum number of nanoseconds to delay.\r
\r
- @return The value of NanoSeconds inputed.\r
+ @return The value of NanoSeconds inputted.\r
\r
**/\r
UINTN\r
#include <Library/ArmDisassemblerLib.h>\r
\r
/**\r
- Place a disassembly of of **OpCodePtr into buffer, and update OpCodePtr to\r
+ Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to\r
point to next instruction.\r
\r
@param OpCodePtrPtr Pointer to pointer of instruction to disassemble.\r
\r
\r
/**\r
- Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to\r
- point to next instructin.\r
+ Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to\r
+ point to next instruction.\r
\r
We cheat and only decode instructions that access\r
memory. If the instruction is not found we dump the instruction in hex.\r
/** @file\r
- Thumb Dissassembler. Still a work in progress.\r
+ Thumb Disassembler. Still a work in progress.\r
\r
Wrong output is a bug, so please fix it.\r
Hex output means there is not yet an entry or a decode bug.\r
} THUMB_INSTRUCTIONS;\r
\r
THUMB_INSTRUCTIONS gOpThumb[] = {\r
-// Thumb 16-bit instrucitons\r
+// Thumb 16-bit instructions\r
// Op Mask Format\r
{ "ADC" , 0x4140, 0xffc0, DATA_FORMAT5 }, // ADC <Rndn>, <Rm>\r
{ "ADR", 0xa000, 0xf800, ADR_FORMAT }, // ADR <Rd>, <label>\r
\r
//\r
// Some instructions specify the PC is always considered aligned\r
-// The PC is after the instruction that is excuting. So you pass\r
+// The PC is after the instruction that is executing. So you pass\r
// in the instruction address and you get back the aligned answer\r
//\r
UINT32\r
}\r
\r
/**\r
- Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to\r
- point to next instructin.\r
+ Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to\r
+ point to next instruction.\r
\r
We cheat and only decode instructions that access\r
memory. If the instruction is not found we dump the instruction in hex.\r
\r
\r
/**\r
- Place a dissasembly of of **OpCodePtr into buffer, and update OpCodePtr to\r
- point to next instructin.\r
+ Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to\r
+ point to next instruction.\r
\r
We cheat and only decode instructions that access\r
memory. If the instruction is not found we dump the instruction in hex.\r
ldr R5, [SP, #0x58] @ PC is the LR pushed by srsfd\r
@ Check to see if we have to adjust for Thumb entry\r
sub r4, r0, #1 @ if (ExceptionType == 1 || ExceptionType == 2)) {\r
- cmp r4, #1 @ // UND & SVC have differnt LR adjust for Thumb\r
+ cmp r4, #1 @ // UND & SVC have different LR adjust for Thumb\r
bhi NoAdjustNeeded\r
\r
tst r1, #0x20 @ if ((CPSR & T)) == T) { // Thumb Mode on entry\r
ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd\r
; Check to see if we have to adjust for Thumb entry\r
sub r4, r0, #1 ; if (ExceptionType == 1 || ExceptionType == 2)) {\r
- cmp r4, #1 ; // UND & SVC have differnt LR adjust for Thumb\r
+ cmp r4, #1 ; // UND & SVC have different LR adjust for Thumb\r
bhi NoAdjustNeeded\r
\r
tst r1, #0x20 ; if ((CPSR & T)) == T) { // Thumb Mode on entry\r
\r
Status = EFI_SUCCESS;\r
\r
- // if we are requested to copy exceptin handlers to another location\r
+ // if we are requested to copy exception handlers to another location\r
if (gArmRelocateVectorTable) {\r
\r
VectorBase = PcdGet64(PcdCpuVectorBaseAddress);\r
}\r
\r
/**\r
-Copies exception handlers to the speciifed address.\r
+Copies exception handlers to the specified address.\r
\r
Caller should try to get an array of interrupt and/or exception vectors that are in use and need to\r
persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.\r
ret\r
\r
\r
-// Keep old function names for C compatibilty for now. Change later?\r
+// Keep old function names for C compatibility for now. Change later?\r
ASM_FUNC(ArmReadTpidrurw)\r
mrs x0, tpidr_el0 // read tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)\r
ret\r
\r
\r
-// Keep old function names for C compatibilty for now. Change later?\r
+// Keep old function names for C compatibility for now. Change later?\r
ASM_FUNC(ArmWriteTpidrurw)\r
msr tpidr_el0, x0 // write tpidr_el0 (v7 TPIDRURW) -> (v8 TPIDR_EL0)\r
ret\r
ret\r
\r
\r
-// Q: id_aa64pfr1_el1 not defined yet. What does this funtion want to access?\r
+// Q: id_aa64pfr1_el1 not defined yet. What does this function want to access?\r
// A: used to setup arch timer. Check if we have security extensions, permissions to set stuff.\r
// See: ArmPkg/Library/ArmArchTimerLib/AArch64/ArmArchTimerLib.c\r
// Not defined yet, but stick in here for now, should read all zeros.\r
\r
\r
ASM_FUNC(ArmIsMpCore)\r
- mrs x0, mpidr_el1 // Read EL1 Mutliprocessor Affinty Reg (MPIDR)\r
+ mrs x0, mpidr_el1 // Read EL1 Multiprocessor Affinty Reg (MPIDR)\r
and x0, x0, #MPIDR_U_MASK // U Bit clear, the processor is part of a multiprocessor system\r
lsr x0, x0, #MPIDR_U_BIT\r
eor x0, x0, #1\r
\r
do {\r
// Get the first Block Entry that matches the Virtual Address and also the information on the Table Descriptor\r
- // such as the the size of the Block Entry and the address of the last BlockEntry of the Table Descriptor\r
+ // such as the size of the Block Entry and the address of the last BlockEntry of the Table Descriptor\r
BlockEntrySize = RegionLength;\r
BlockEntry = GetBlockEntryListFromAddress (RootTable, RegionStart, &TableLevel, &BlockEntrySize, &LastBlockEntry);\r
if (BlockEntry == NULL) {\r
for(i=0; i<NumSections; i++) {\r
CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];\r
\r
- // has this descriptor already been coverted to pages?\r
+ // has this descriptor already been converted to pages?\r
if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(CurrentDescriptor)) {\r
// forward this 1MB range to page table function instead\r
Status = UpdatePageEntries (\r
#/** @file\r
-# PeCoff extra action libary for DXE phase that run Unix emulator.\r
+# PeCoff extra action library for DXE phase that run Unix emulator.\r
#\r
# Lib to provide memory journal status code reporting Routines\r
# Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>\r
/**\r
This is the default action to take on an unexpected exception\r
\r
- Since this is exception context don't do anything crazy like try to allcoate memory.\r
+ Since this is exception context don't do anything crazy like try to allocate memory.\r
\r
@param ExceptionType Type of the exception\r
@param SystemContext Register state at the time of the Exception\r
/**\r
This is the default action to take on an unexpected exception\r
\r
- Since this is exception context don't do anything crazy like try to allcoate memory.\r
+ Since this is exception context don't do anything crazy like try to allocate memory.\r
\r
@param ExceptionType Type of the exception\r
@param SystemContext Register state at the time of the Exception\r
Do the platform specific action after the console is ready\r
Possible things that can be done in PlatformBootManagerAfterConsole:\r
> Console post action:\r
- > Dynamically switch output mode from 100x31 to 80x25 for certain senarino\r
+ > Dynamically switch output mode from 100x31 to 80x25 for certain scenario\r
> Signal console ready platform customized event\r
> Run diagnostics like memory testing\r
> Connect certain devices\r
- > Dispatch aditional option roms\r
+ > Dispatch additional option roms\r
> Special boot: e.g.: USB boot, enter UI\r
**/\r
VOID\r
/**\r
Append string to debugger script file, create file if needed.\r
\r
- This library can show up in mulitple places so we need to append the file every time we write to it.\r
+ This library can show up in multiple places so we need to append the file every time we write to it.\r
For example Sec can use this to load the DXE core, and the DXE core would use this to load all the\r
other modules. So we have two instances of the library in the system.\r
\r
#/** @file\r
-# PeCoff extra action libary for DXE phase that run Unix emulator.\r
+# PeCoff extra action library for DXE phase that run Unix emulator.\r
#\r
# Lib to provide memory journal status code reporting Routines\r
# Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>\r
\r
Print a message of the form "ASSERT <FileName>(<LineNumber>): <Description>\n"\r
to the debug output device. If DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED bit of\r
- PcdDebugProperyMask is set then CpuBreakpoint() is called. Otherwise, if\r
- DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugProperyMask is set then\r
+ PcdDebugPropertyMask is set then CpuBreakpoint() is called. Otherwise, if\r
+ DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED bit of PcdDebugPropertyMask is set then\r
CpuDeadLoop() is called. If neither of these bits are set, then this function\r
returns immediately after the message is printed to the debug output device.\r
- DebugAssert() must actively prevent recusrsion. If DebugAssert() is called while\r
+ DebugAssert() must actively prevent recursion. If DebugAssert() is called while\r
processing another DebugAssert(), then DebugAssert() must return immediately.\r
\r
If FileName is NULL, then a <FileName> string of "(NULL) Filename" is printed.\r
ASSERT (Buffer != NULL);\r
\r
//\r
- // SetMem() checks for the the ASSERT() condition on Length and returns Buffer\r
+ // SetMem() checks for the ASSERT() condition on Length and returns Buffer\r
//\r
return SetMem (Buffer, Length, PcdGet8(PcdDebugClearMemoryValue));\r
}\r
Returns TRUE if ASSERT() macros are enabled.\r
\r
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of\r
- PcdDebugProperyMask is set. Otherwise FALSE is returned.\r
+ PcdDebugPropertyMask is set. Otherwise FALSE is returned.\r
\r
- @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is set.\r
- @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugProperyMask is clear.\r
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugPropertyMask is set.\r
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED bit of PcdDebugPropertyMask is clear.\r
\r
**/\r
BOOLEAN\r
Returns TRUE if DEBUG()macros are enabled.\r
\r
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of\r
- PcdDebugProperyMask is set. Otherwise FALSE is returned.\r
+ PcdDebugPropertyMask is set. Otherwise FALSE is returned.\r
\r
- @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is set.\r
- @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugProperyMask is clear.\r
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugPropertyMask is set.\r
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_PRINT_ENABLED bit of PcdDebugPropertyMask is clear.\r
\r
**/\r
BOOLEAN\r
Returns TRUE if DEBUG_CODE()macros are enabled.\r
\r
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of\r
- PcdDebugProperyMask is set. Otherwise FALSE is returned.\r
+ PcdDebugPropertyMask is set. Otherwise FALSE is returned.\r
\r
- @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is set.\r
- @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugProperyMask is clear.\r
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugPropertyMask is set.\r
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_CODE_ENABLED bit of PcdDebugPropertyMask is clear.\r
\r
**/\r
BOOLEAN\r
Returns TRUE if DEBUG_CLEAR_MEMORY()macro is enabled.\r
\r
This function returns TRUE if the DEBUG_PROPERTY_DEBUG_CLEAR_MEMORY_ENABLED bit of\r
- PcdDebugProperyMask is set. Otherwise FALSE is returned.\r
+ PcdDebugPropertyMask is set. Otherwise FALSE is returned.\r
\r
- @retval TRUE The DEBUG_PROPERTY_DEBUG_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is set.\r
- @retval FALSE The DEBUG_PROPERTY_DEBUG_CLEAR_MEMORY_ENABLED bit of PcdDebugProperyMask is clear.\r
+ @retval TRUE The DEBUG_PROPERTY_DEBUG_CLEAR_MEMORY_ENABLED bit of PcdDebugPropertyMask is set.\r
+ @retval FALSE The DEBUG_PROPERTY_DEBUG_CLEAR_MEMORY_ENABLED bit of PcdDebugPropertyMask is clear.\r
\r
**/\r
BOOLEAN\r
#/** @file\r
-# Semihosting serail port lib\r
+# Semihosting serial port lib\r
#\r
# Copyright (c) 2008, Apple Inc. All rights reserved.<BR>\r
#\r
@param NumberOfBytes Number of output bytes which are cached in Buffer.\r
\r
@retval 0 Read data failed.\r
- @retval !0 Aactual number of bytes read from serial device.\r
+ @retval !0 Actual number of bytes read from serial device.\r
\r
**/\r
UINTN\r
\r
\r
/**\r
- Check to see if any data is avaiable to be read from the debug device.\r
+ Check to see if any data is available to be read from the debug device.\r
\r
- @retval TRUE At least one byte of data is avaiable to be read\r
- @retval FALSE No data is avaiable to be read\r
+ @retval TRUE At least one byte of data is available to be read\r
+ @retval FALSE No data is available to be read\r
\r
**/\r
BOOLEAN\r
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