/** @file\r
- Macros to work around lack of Apple support for LDR register, =expr\r
+ Macros to work around lack of Clang support for LDR register, =expr\r
\r
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r
#ifndef __MACRO_IO_LIBV8_H__\r
#define __MACRO_IO_LIBV8_H__\r
\r
-#if defined (__GNUC__)\r
-\r
-#define MmioWrite32(Address, Data) \\r
- ldr x1, =Address ; \\r
- ldr w0, =Data ; \\r
- str w0, [x1]\r
-\r
-#define MmioOr32(Address, OrData) \\r
- ldr x1, =Address ; \\r
- ldr w2, =OrData ; \\r
- ldr w0, [x1] ; \\r
- orr w0, w0, w2 ; \\r
- str w0, [x1]\r
-\r
-#define MmioAnd32(Address, AndData) \\r
- ldr x1, =Address ; \\r
- ldr w2, =AndData ; \\r
- ldr w0, [x1] ; \\r
- and w0, w0, w2 ; \\r
- str w0, [x1]\r
-\r
-#define MmioAndThenOr32(Address, AndData, OrData) \\r
- ldr x1, =Address ; \\r
- ldr w0, [x1] ; \\r
- ldr w2, =AndData ; \\r
- and w0, w0, w2 ; \\r
- ldr w2, =OrData ; \\r
- orr w0, w0, w2 ; \\r
- str w0, [x1]\r
-\r
-#define MmioWriteFromReg32(Address, Reg) \\r
- ldr x1, =Address ; \\r
- str Reg, [x1]\r
-\r
-#define MmioRead32(Address) \\r
- ldr x1, =Address ; \\r
- ldr w0, [x1]\r
-\r
-#define MmioReadToReg32(Address, Reg) \\r
- ldr x1, =Address ; \\r
- ldr Reg, [x1]\r
-\r
-#define LoadConstant(Data) \\r
- ldr x0, =Data\r
-\r
-#define LoadConstantToReg(Data, Reg) \\r
- ldr Reg, =Data\r
-\r
#define SetPrimaryStack(StackTop, GlobalSize, Tmp, Tmp1) \\r
ands Tmp, GlobalSize, #15 ; \\r
mov Tmp1, #16 ; \\r
// Provide the Macro with a safe temp xreg to use.\r
#define EL1_OR_EL2(SAFE_XREG) \\r
mrs SAFE_XREG, CurrentEL ;\\r
- cmp SAFE_XREG, #0x4 ;\\r
- b.eq 1f ;\\r
- cmp SAFE_XREG, #0x8 ;\\r
- b.eq 2f ;\\r
- b dead ;// We should never get here.\r
+ cmp SAFE_XREG, #0x8 ;\\r
+ b.eq 2f ;\\r
+ cmp SAFE_XREG, #0x4 ;\\r
+ b.ne . ;// We should never get here\r
+// EL1 code starts here\r
\r
// CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1\r
// This only selects between EL1 and EL2 and EL3, else we die.\r
// Provide the Macro with a safe temp xreg to use.\r
-#define EL1_OR_EL2_OR_EL3(SAFE_XREG) \\r
+#define EL1_OR_EL2_OR_EL3(SAFE_XREG) \\r
mrs SAFE_XREG, CurrentEL ;\\r
+ cmp SAFE_XREG, #0xC ;\\r
+ b.eq 3f ;\\r
+ cmp SAFE_XREG, #0x8 ;\\r
+ b.eq 2f ;\\r
cmp SAFE_XREG, #0x4 ;\\r
- b.eq 1f ;\\r
- cmp SAFE_XREG, #0x8 ;\\r
- b.eq 2f ;\\r
- cmp SAFE_XREG, #0xC ;\\r
- b.eq 3f ;\\r
- b dead ;// We should never get here.\r
+ b.ne . ;// We should never get here\r
+// EL1 code starts here\r
+#if defined(__clang__)\r
+\r
+// load x0 with _Data\r
+#define LoadConstant(_Data) \\r
+ ldr x0, 1f ; \\r
+ b 2f ; \\r
+.align(8) ; \\r
+1: \\r
+ .8byte (_Data) ; \\r
+2:\r
+\r
+// load _Reg with _Data\r
+#define LoadConstantToReg(_Data, _Reg) \\r
+ ldr _Reg, 1f ; \\r
+ b 2f ; \\r
+.align(8) ; \\r
+1: \\r
+ .8byte (_Data) ; \\r
+2:\r
+\r
+#elif defined (__GNUC__)\r
\r
-#else\r
+#define LoadConstant(Data) \\r
+ ldr x0, =Data\r
\r
-#error RVCT AArch64 tool chain is not supported\r
+#define LoadConstantToReg(Data, Reg) \\r
+ ldr Reg, =Data\r
\r
-#endif // __GNUC__ \r
+#endif // __GNUC__\r
\r
#endif // __MACRO_IO_LIBV8_H__\r
\r