ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ArmCortexA9Lib.inf\r
ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf\r
\r
-# ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf\r
-# ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf\r
-# ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf\r
-# ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf\r
ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf\r
ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf\r
\r
+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <Base.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/ArmCpuLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/PcdLib.h>\r
-\r
-VOID\r
-ArmCpuSetup (\r
- IN UINTN MpId\r
- )\r
-{\r
- ASSERT(0); //TODO: Implement me\r
-}\r
-\r
-\r
-VOID\r
-ArmCpuSetupSmpNonSecure (\r
- IN UINTN MpId\r
- )\r
-{\r
- ASSERT(0); //TODO: Implement me\r
-}\r
-\r
+++ /dev/null
-#/* @file\r
-# Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = Arm11MpCoreLib\r
- FILE_GUID = dc8a69e0-6be0-469c-94d3-5e6d71aa9808\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmCpuLib\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- ArmPkg/ArmPkg.dec\r
-\r
-[LibraryClasses]\r
- ArmLib\r
- IoLib\r
- PcdLib\r
-\r
-[Sources.common]\r
- Arm11Lib.c\r
#include <Uefi/UefiBaseType.h>\r
\r
#ifdef MDE_CPU_ARM\r
- #ifdef ARM_CPU_ARMv6\r
- #include <Chipset/ARM1176JZ-S.h>\r
- #else\r
- #include <Chipset/ArmV7.h>\r
- #endif\r
+ #include <Chipset/ArmV7.h>\r
#elif defined(MDE_CPU_AARCH64)\r
#include <Chipset/AArch64.h>\r
#else\r
+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
- Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <Chipset/ARM1176JZ-S.h>\r
-\r
-#include <Library/ArmLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
-\r
-VOID\r
-EFIAPI\r
-ArmWriteVBar (\r
- IN UINTN VectorBase\r
- )\r
-{\r
- ASSERT(FeaturePcdGet (PcdRelocateVectorTable) == TRUE);\r
-\r
- if (VectorBase == 0x0) {\r
- ArmSetLowVectors ();\r
- } else if (VectorBase == 0xFFFF0000) {\r
- ArmSetHighVectors ();\r
- } else {\r
- // Feature not supported by ARM11. The Vector Table is either at 0x0 or 0xFFFF0000\r
- ASSERT(0);\r
- }\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-ArmReadVBar (\r
- VOID\r
- )\r
-{\r
- ASSERT((FeaturePcdGet (PcdRelocateVectorTable) == TRUE) && ((PcdGet32 (PcdCpuVectorBaseAddress) == 0x0) || (PcdGet32 (PcdCpuVectorBaseAddress) == 0xFFFF0000)));\r
- return PcdGet32 (PcdCpuVectorBaseAddress);\r
-}\r
-\r
+++ /dev/null
-#/** @file\r
-# Semihosting serail port lib\r
-#\r
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = Arm11ArmLib\r
- FILE_GUID = 00586300-0E06-4790-AC44-86C56ACBB942\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmLib\r
-\r
-[Sources.common]\r
- ../Common/Arm/ArmLibSupport.S | GCC\r
- ../Common/Arm/ArmLibSupport.asm | RVCT\r
- ../Common/ArmLib.c\r
-\r
- Arm11Support.S | GCC\r
- Arm11Support.asm | RVCT\r
-\r
- Arm11Lib.c\r
- Arm11LibMem.c\r
- ../Arm9/Arm9CacheInformation.c\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- MemoryAllocationLib\r
-\r
-[Protocols]\r
- gEfiCpuArchProtocolGuid\r
-\r
-[FeaturePcd]\r
- gArmTokenSpaceGuid.PcdRelocateVectorTable\r
-\r
-[FixedPcd]\r
- gArmTokenSpaceGuid.PcdCpuVectorBaseAddress\r
+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
- Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <Chipset/ARM1176JZ-S.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-\r
-VOID\r
-FillTranslationTable (\r
- IN UINT32 *TranslationTable,\r
- IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion\r
- )\r
-{\r
- UINT32 *Entry;\r
- UINTN Sections;\r
- UINTN Index;\r
- UINT32 Attributes;\r
- UINT32 PhysicalBase = MemoryRegion->PhysicalBase;\r
-\r
- switch (MemoryRegion->Attributes) {\r
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);\r
- break;\r
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);\r
- break;\r
- case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);\r
- break;\r
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);\r
- break;\r
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);\r
- break;\r
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);\r
- break;\r
- default:\r
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);\r
- break;\r
- }\r
-\r
- Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);\r
- Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 );\r
-\r
- for (Index = 0; Index < Sections; Index++)\r
- {\r
- *Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;\r
- PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;\r
- }\r
-}\r
-\r
-RETURN_STATUS\r
-EFIAPI\r
-ArmConfigureMmu (\r
- IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r
- OUT VOID **TranslationTableBase OPTIONAL,\r
- OUT UINTN *TranslationTableSize OPTIONAL\r
- )\r
-{\r
- VOID *TranslationTable;\r
-\r
- // Allocate pages for translation table.\r
- TranslationTable = AllocatePages (EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));\r
- if (TranslationTable == NULL) {\r
- return RETURN_OUT_OF_RESOURCES;\r
- }\r
- TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);\r
-\r
- if (TranslationTableBase != NULL) {\r
- *TranslationTableBase = TranslationTable;\r
- }\r
-\r
- if (TranslationTableBase != NULL) {\r
- *TranslationTableSize = TRANSLATION_TABLE_SIZE;\r
- }\r
-\r
- ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);\r
-\r
- ArmCleanInvalidateDataCache();\r
- ArmInvalidateInstructionCache();\r
- ArmInvalidateTlb();\r
-\r
- ArmDisableDataCache();\r
- ArmDisableInstructionCache();\r
- ArmDisableMmu();\r
-\r
- // Make sure nothing sneaked into the cache\r
- ArmCleanInvalidateDataCache();\r
- ArmInvalidateInstructionCache();\r
-\r
- while (MemoryTable->Length != 0) {\r
- FillTranslationTable(TranslationTable, MemoryTable);\r
- MemoryTable++;\r
- }\r
-\r
- ArmSetTTBR0(TranslationTable);\r
-\r
- ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |\r
- DOMAIN_ACCESS_CONTROL_NONE(14) |\r
- DOMAIN_ACCESS_CONTROL_NONE(13) |\r
- DOMAIN_ACCESS_CONTROL_NONE(12) |\r
- DOMAIN_ACCESS_CONTROL_NONE(11) |\r
- DOMAIN_ACCESS_CONTROL_NONE(10) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 9) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 8) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 7) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 6) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 5) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 4) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 3) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 2) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 1) |\r
- DOMAIN_ACCESS_CONTROL_MANAGER(0));\r
-\r
- ArmEnableInstructionCache();\r
- ArmEnableDataCache();\r
- ArmEnableMmu();\r
-\r
- return RETURN_SUCCESS;\r
-}\r
+++ /dev/null
-#/** @file\r
-# Semihosting serail port lib\r
-#\r
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = Arm11ArmLib\r
- FILE_GUID = 8dfb4ea2-3901-44f9-ae54-ca3d50362d2f\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmLib\r
-\r
-[Sources.common]\r
- ../Common/Arm/ArmLibSupport.S | GCC\r
- ../Common/Arm/ArmLibSupport.asm | RVCT\r
- ../Common/ArmLib.c\r
-\r
- Arm11Support.S | GCC\r
- Arm11Support.asm | RVCT\r
-\r
- Arm11Lib.c\r
- Arm11LibMem.c\r
- ../Arm9/Arm9CacheInformation.c\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- PrePiLib\r
-\r
-[Protocols]\r
- gEfiCpuArchProtocolGuid\r
-\r
-[FeaturePcd]\r
- gArmTokenSpaceGuid.PcdRelocateVectorTable\r
-\r
-[FixedPcd]\r
- gArmTokenSpaceGuid.PcdCpuVectorBaseAddress\r
+++ /dev/null
-#/** @file\r
-# Semihosting serail port lib\r
-#\r
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = Arm11LibSec\r
- FILE_GUID = bfecdbc7-a860-4993-bc09-8e3ea762a758\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmLib\r
-\r
-[Sources.common]\r
- ../Common/Arm/ArmLibSupport.S | GCC\r
- ../Common/Arm/ArmLibSupport.asm | RVCT\r
- ../Common/ArmLib.c\r
-\r
- Arm11Support.S | GCC\r
- Arm11Support.asm | RVCT\r
-\r
- Arm11Lib.c\r
- ../Arm9/Arm9CacheInformation.c\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- MdePkg/MdePkg.dec\r
-\r
-[Protocols]\r
- gEfiCpuArchProtocolGuid\r
-\r
-[FeaturePcd]\r
- gArmTokenSpaceGuid.PcdRelocateVectorTable\r
-\r
-[FixedPcd]\r
- gArmTokenSpaceGuid.PcdCpuVectorBaseAddress\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-#include <AsmMacroIoLib.h>\r
-\r
-.text\r
-.align 2\r
-GCC_ASM_EXPORT(ArmDisableCachesAndMmu)\r
-GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)\r
-GCC_ASM_EXPORT(ArmCleanDataCache)\r
-GCC_ASM_EXPORT(ArmInvalidateDataCache)\r
-GCC_ASM_EXPORT(ArmInvalidateInstructionCache)\r
-GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)\r
-GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)\r
-GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)\r
-GCC_ASM_EXPORT(ArmEnableMmu)\r
-GCC_ASM_EXPORT(ArmDisableMmu)\r
-GCC_ASM_EXPORT(ArmMmuEnabled)\r
-GCC_ASM_EXPORT(ArmEnableDataCache)\r
-GCC_ASM_EXPORT(ArmDisableDataCache)\r
-GCC_ASM_EXPORT(ArmEnableInstructionCache)\r
-GCC_ASM_EXPORT(ArmDisableInstructionCache)\r
-GCC_ASM_EXPORT(ArmEnableBranchPrediction)\r
-GCC_ASM_EXPORT(ArmDisableBranchPrediction)\r
-GCC_ASM_EXPORT(ArmDataMemoryBarrier)\r
-GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)\r
-GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)\r
-GCC_ASM_EXPORT(ArmSetLowVectors)\r
-GCC_ASM_EXPORT(ArmSetHighVectors)\r
-GCC_ASM_EXPORT(ArmIsMpCore)\r
-GCC_ASM_EXPORT(ArmCallWFI)\r
-GCC_ASM_EXPORT(ArmReadMpidr)\r
-GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)\r
-GCC_ASM_EXPORT(ArmEnableFiq)\r
-GCC_ASM_EXPORT(ArmDisableFiq)\r
-GCC_ASM_EXPORT(ArmEnableInterrupts)\r
-GCC_ASM_EXPORT(ArmDisableInterrupts)\r
-GCC_ASM_EXPORT (ArmEnableVFP)\r
-\r
-Arm11PartNumberMask: .word 0xFFF0\r
-Arm11PartNumber: .word 0xB020\r
-\r
-.set DC_ON, (0x1<<2)\r
-.set IC_ON, (0x1<<12)\r
-.set XP_ON, (0x1<<23)\r
-.set CTRL_M_BIT, (1 << 0)\r
-.set CTRL_C_BIT, (1 << 2)\r
-.set CTRL_I_BIT, (1 << 12)\r
-\r
-ASM_PFX(ArmDisableCachesAndMmu):\r
- mrc p15, 0, r0, c1, c0, 0 @ Get control register\r
- bic r0, r0, #CTRL_M_BIT @ Disable MMU\r
- bic r0, r0, #CTRL_C_BIT @ Disable D Cache\r
- bic r0, r0, #CTRL_I_BIT @ Disable I Cache\r
- mcr p15, 0, r0, c1, c0, 0 @ Write control register\r
- bx LR\r
-\r
-ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r
- mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line\r
- bx lr\r
-\r
-\r
-ASM_PFX(ArmCleanDataCacheEntryByMVA):\r
- mcr p15, 0, r0, c7, c10, 1 @clean single data cache line\r
- bx lr\r
-\r
-\r
-ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):\r
- mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line\r
- bx lr\r
-\r
-\r
-ASM_PFX(ArmCleanDataCache):\r
- mcr p15, 0, r0, c7, c10, 0 @ clean entire data cache\r
- bx lr\r
-\r
-\r
-ASM_PFX(ArmCleanInvalidateDataCache):\r
- mcr p15, 0, r0, c7, c14, 0 @ clean and invalidate entire data cache\r
- bx lr\r
-\r
-\r
-ASM_PFX(ArmInvalidateDataCache):\r
- mcr p15, 0, r0, c7, c6, 0 @ invalidate entire data cache\r
- bx lr\r
-\r
-\r
-ASM_PFX(ArmInvalidateInstructionCache):\r
- mcr p15, 0, r0, c7, c5, 0 @invalidate entire instruction cache\r
- mov R0,#0\r
- mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer\r
- bx lr\r
-\r
-ASM_PFX(ArmEnableMmu):\r
- mrc p15,0,R0,c1,c0,0\r
- orr R0,R0,#1\r
- mcr p15,0,R0,c1,c0,0\r
- bx LR\r
-\r
-ASM_PFX(ArmMmuEnabled):\r
- mrc p15,0,R0,c1,c0,0\r
- and R0,R0,#1\r
- bx LR\r
-\r
-ASM_PFX(ArmDisableMmu):\r
- mrc p15,0,R0,c1,c0,0\r
- bic R0,R0,#1\r
- mcr p15,0,R0,c1,c0,0\r
- mov R0,#0\r
- mcr p15,0,R0,c7,c10,4 @Data synchronization barrier\r
- mov R0,#0\r
- mcr p15,0,R0,c7,c5,4 @Flush Prefetch buffer\r
- bx LR\r
-\r
-ASM_PFX(ArmEnableDataCache):\r
- LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON\r
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
- orr R0,R0,R1 @Set C bit\r
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
- bx LR\r
-\r
-ASM_PFX(ArmDisableDataCache):\r
- LoadConstantToReg(DC_ON, R1) @ldr R1,=DC_ON\r
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
- bic R0,R0,R1 @Clear C bit\r
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
- bx LR\r
-\r
-ASM_PFX(ArmEnableInstructionCache):\r
- ldr R1,=IC_ON\r
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
- orr R0,R0,R1 @Set I bit\r
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
- bx LR\r
-\r
-ASM_PFX(ArmDisableInstructionCache):\r
- ldr R1,=IC_ON\r
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
- bic R0,R0,R1 @Clear I bit.\r
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
- bx LR\r
-\r
-ASM_PFX(ArmEnableBranchPrediction):\r
- mrc p15, 0, r0, c1, c0, 0\r
- orr r0, r0, #0x00000800\r
- mcr p15, 0, r0, c1, c0, 0\r
- bx LR\r
-\r
-ASM_PFX(ArmDisableBranchPrediction):\r
- mrc p15, 0, r0, c1, c0, 0\r
- bic r0, r0, #0x00000800\r
- mcr p15, 0, r0, c1, c0, 0\r
- bx LR\r
-\r
-ASM_PFX(ArmDataMemoryBarrier):\r
- mov R0, #0\r
- mcr P15, #0, R0, C7, C10, #5\r
- bx LR\r
-\r
-ASM_PFX(ArmDataSyncronizationBarrier):\r
- mov R0, #0\r
- mcr P15, #0, R0, C7, C10, #4\r
- bx LR\r
-\r
-ASM_PFX(ArmInstructionSynchronizationBarrier):\r
- mov R0, #0\r
- mcr P15, #0, R0, C7, C5, #4\r
- bx LR\r
-\r
-ASM_PFX(ArmSetLowVectors):\r
- mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
- bic r0, r0, #0x00002000 @ clear V bit\r
- mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r
- bx LR\r
-\r
-ASM_PFX(ArmSetHighVectors):\r
- mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)\r
- orr r0, r0, #0x00002000 @ clear V bit\r
- mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)\r
- bx LR\r
-\r
-ASM_PFX(ArmIsMpCore):\r
- push { r1 }\r
- mrc p15, 0, r0, c0, c0, 0\r
- # Extract Part Number to check it is an ARM11MP core (0xB02)\r
- LoadConstantToReg (Arm11PartNumberMask, r1)\r
- and r0, r0, r1\r
- LoadConstantToReg (Arm11PartNumber, r1)\r
- cmp r0, r1\r
- movne r0, #0\r
- pop { r1 }\r
- bx lr\r
-\r
-ASM_PFX(ArmCallWFI):\r
- wfi\r
- bx lr\r
-\r
-ASM_PFX(ArmReadMpidr):\r
- mrc p15, 0, r0, c0, c0, 5 @ read MPIDR\r
- bx lr\r
-\r
-ASM_PFX(ArmEnableFiq):\r
- mrs R0,CPSR\r
- bic R0,R0,#0x40 @Enable FIQ interrupts\r
- msr CPSR_c,R0\r
- bx LR\r
-\r
-ASM_PFX(ArmDisableFiq):\r
- mrs R0,CPSR\r
- orr R1,R0,#0x40 @Disable FIQ interrupts\r
- msr CPSR_c,R1\r
- tst R0,#0x80\r
- moveq R0,#1\r
- movne R0,#0\r
- bx LR\r
-\r
-ASM_PFX(ArmEnableInterrupts):\r
- mrs R0,CPSR\r
- bic R0,R0,#0x80 @Enable IRQ interrupts\r
- msr CPSR_c,R0\r
- bx LR\r
-\r
-ASM_PFX(ArmDisableInterrupts):\r
- mrs R0,CPSR\r
- orr R1,R0,#0x80 @Disable IRQ interrupts\r
- msr CPSR_c,R1\r
- tst R0,#0x80\r
- moveq R0,#1\r
- movne R0,#0\r
- bx LR\r
-\r
-ASM_PFX(ArmEnableVFP):\r
- # Read CPACR (Coprocessor Access Control Register)\r
- mrc p15, 0, r0, c1, c0, 2\r
- # Enable VPF access (Full Access to CP10, CP11) (V* instructions)\r
- orr r0, r0, #0x00f00000\r
- # Write back CPACR (Coprocessor Access Control Register)\r
- mcr p15, 0, r0, c1, c0, 2\r
- # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.\r
- mov r0, #0x40000000\r
- #TODO: Fixme - need compilation flag\r
- #fmxr FPEXC, r0\r
- bx lr\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
+++ /dev/null
-//------------------------------------------------------------------------------\r
-//\r
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
- EXPORT ArmCleanInvalidateDataCache\r
- EXPORT ArmCleanDataCache\r
- EXPORT ArmInvalidateDataCache\r
- EXPORT ArmInvalidateInstructionCache\r
- EXPORT ArmInvalidateDataCacheEntryByMVA\r
- EXPORT ArmCleanDataCacheEntryByMVA\r
- EXPORT ArmCleanInvalidateDataCacheEntryByMVA\r
- EXPORT ArmEnableMmu\r
- EXPORT ArmDisableMmu\r
- EXPORT ArmMmuEnabled\r
- EXPORT ArmEnableDataCache\r
- EXPORT ArmDisableDataCache\r
- EXPORT ArmEnableInstructionCache\r
- EXPORT ArmDisableInstructionCache\r
- EXPORT ArmEnableBranchPrediction\r
- EXPORT ArmDisableBranchPrediction\r
- EXPORT ArmDataMemoryBarrier\r
- EXPORT ArmDataSyncronizationBarrier\r
- EXPORT ArmInstructionSynchronizationBarrier\r
-\r
-\r
-DC_ON EQU ( 0x1:SHL:2 )\r
-IC_ON EQU ( 0x1:SHL:12 )\r
-XP_ON EQU ( 0x1:SHL:23 )\r
-\r
-\r
- AREA ArmCacheLib, CODE, READONLY\r
- PRESERVE8\r
-\r
-\r
-ArmInvalidateDataCacheEntryByMVA\r
- mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line\r
- bx lr\r
-\r
-\r
-ArmCleanDataCacheEntryByMVA\r
- mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line\r
- bx lr\r
-\r
-\r
-ArmCleanInvalidateDataCacheEntryByMVA\r
- mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line\r
- bx lr\r
-\r
-\r
-ArmCleanDataCache\r
- mcr p15, 0, r0, c7, c10, 0 ; clean entire data cache\r
- bx lr\r
-\r
-\r
-ArmCleanInvalidateDataCache\r
- mcr p15, 0, r0, c7, c14, 0 ; clean and invalidate entire data cache\r
- bx lr\r
-\r
-\r
-ArmInvalidateDataCache\r
- mcr p15, 0, r0, c7, c6, 0 ; invalidate entire data cache\r
- bx lr\r
-\r
-\r
-ArmInvalidateInstructionCache\r
- mcr p15, 0, r0, c7, c5, 0 ;invalidate entire instruction cache\r
- mov R0,#0\r
- mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer\r
- bx lr\r
-\r
-ArmEnableMmu\r
- mrc p15,0,R0,c1,c0,0\r
- orr R0,R0,#1\r
- mcr p15,0,R0,c1,c0,0\r
- bx LR\r
-\r
-ArmMmuEnabled\r
- mrc p15,0,R0,c1,c0,0\r
- and R0,R0,#1\r
- bx LR\r
-\r
-ArmDisableMmu\r
- mrc p15,0,R0,c1,c0,0\r
- bic R0,R0,#1\r
- mcr p15,0,R0,c1,c0,0\r
- mov R0,#0\r
- mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier\r
- mov R0,#0\r
- mcr p15,0,R0,c7,c5,4 ;Flush Prefetch buffer\r
- bx LR\r
-\r
-ArmEnableDataCache\r
- LDR R1,=DC_ON\r
- MRC p15,0,R0,c1,c0,0 ;Read control register configuration data\r
- ORR R0,R0,R1 ;Set C bit\r
- MCR p15,0,r0,c1,c0,0 ;Write control register configuration data\r
- BX LR\r
-\r
-ArmDisableDataCache\r
- LDR R1,=DC_ON\r
- MRC p15,0,R0,c1,c0,0 ;Read control register configuration data\r
- BIC R0,R0,R1 ;Clear C bit\r
- MCR p15,0,r0,c1,c0,0 ;Write control register configuration data\r
- BX LR\r
-\r
-ArmEnableInstructionCache\r
- LDR R1,=IC_ON\r
- MRC p15,0,R0,c1,c0,0 ;Read control register configuration data\r
- ORR R0,R0,R1 ;Set I bit\r
- MCR p15,0,r0,c1,c0,0 ;Write control register configuration data\r
- BX LR\r
-\r
-ArmDisableInstructionCache\r
- LDR R1,=IC_ON\r
- MRC p15,0,R0,c1,c0,0 ;Read control register configuration data\r
- BIC R0,R0,R1 ;Clear I bit.\r
- MCR p15,0,r0,c1,c0,0 ;Write control register configuration data\r
- BX LR\r
-\r
-ArmEnableBranchPrediction\r
- mrc p15, 0, r0, c1, c0, 0\r
- orr r0, r0, #0x00000800\r
- mcr p15, 0, r0, c1, c0, 0\r
- bx LR\r
-\r
-ArmDisableBranchPrediction\r
- mrc p15, 0, r0, c1, c0, 0\r
- bic r0, r0, #0x00000800\r
- mcr p15, 0, r0, c1, c0, 0\r
- bx LR\r
-\r
-ASM_PFX(ArmDataMemoryBarrier):\r
- mov R0, #0\r
- mcr P15, #0, R0, C7, C10, #5\r
- bx LR\r
-\r
-ASM_PFX(ArmDataSyncronizationBarrier):\r
- mov R0, #0\r
- mcr P15, #0, R0, C7, C10, #4\r
- bx LR\r
-\r
-ASM_PFX(ArmInstructionSynchronizationBarrier):\r
- MOV R0, #0\r
- MCR P15, #0, R0, C7, C5, #4\r
- bx LR\r
-\r
- END\r
\r
#include <AsmMacroIoLib.h>\r
\r
-#ifdef ARM_CPU_ARMv6\r
-// No memory barriers for ARMv6\r
-#define isb\r
-#define dsb\r
-#endif\r
-\r
.text\r
.align 2\r
GCC_ASM_EXPORT(ArmReadMidr)\r
\r
INCLUDE AsmMacroIoLib.inc\r
\r
-#ifdef ARM_CPU_ARMv6\r
-// No memory barriers for ARMv6\r
-#define isb\r
-#define dsb\r
-#endif\r
-\r
EXPORT ArmReadMidr\r
EXPORT ArmCacheInfo\r
EXPORT ArmGetInterruptState\r
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