1 #------------------------------------------------------------------------------
3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
6 # This program and the accompanying materials
7 # are licensed and made available under the terms and conditions of the BSD License
8 # which accompanies this distribution. The full text of the license may be found at
9 # http://opensource.org/licenses/bsd-license.php
11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 #------------------------------------------------------------------------------
16 #include <AsmMacroIoLib.h>
20 GCC_ASM_EXPORT(ArmReadMidr)
21 GCC_ASM_EXPORT(ArmCacheInfo)
22 GCC_ASM_EXPORT(ArmGetInterruptState)
23 GCC_ASM_EXPORT(ArmGetFiqState)
24 GCC_ASM_EXPORT(ArmGetTTBR0BaseAddress)
25 GCC_ASM_EXPORT(ArmSetTTBR0)
26 GCC_ASM_EXPORT(ArmSetDomainAccessControl)
27 GCC_ASM_EXPORT(CPSRMaskInsert)
28 GCC_ASM_EXPORT(CPSRRead)
29 GCC_ASM_EXPORT(ArmReadCpacr)
30 GCC_ASM_EXPORT(ArmWriteCpacr)
31 GCC_ASM_EXPORT(ArmWriteAuxCr)
32 GCC_ASM_EXPORT(ArmReadAuxCr)
33 GCC_ASM_EXPORT(ArmInvalidateTlb)
34 GCC_ASM_EXPORT(ArmUpdateTranslationTableEntry)
35 GCC_ASM_EXPORT(ArmReadScr)
36 GCC_ASM_EXPORT(ArmWriteScr)
37 GCC_ASM_EXPORT(ArmReadMVBar)
38 GCC_ASM_EXPORT(ArmWriteMVBar)
39 GCC_ASM_EXPORT(ArmReadHVBar)
40 GCC_ASM_EXPORT(ArmWriteHVBar)
41 GCC_ASM_EXPORT(ArmCallWFE)
42 GCC_ASM_EXPORT(ArmCallSEV)
43 GCC_ASM_EXPORT(ArmReadSctlr)
44 GCC_ASM_EXPORT(ArmReadCpuActlr)
45 GCC_ASM_EXPORT(ArmWriteCpuActlr)
47 #------------------------------------------------------------------------------
53 ASM_PFX(ArmCacheInfo):
57 ASM_PFX(ArmGetInterruptState):
59 tst R0,#0x80 @Check if IRQ is enabled.
64 ASM_PFX(ArmGetFiqState):
66 tst R0,#0x40 @Check if FIQ is enabled.
71 ASM_PFX(ArmSetDomainAccessControl):
75 ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
76 stmfd sp!, {r4-r12, lr} @ save all the banked registers
77 mov r3, sp @ copy the stack pointer into a non-banked register
78 mrs r2, cpsr @ read the cpsr
79 bic r2, r2, r0 @ clear mask in the cpsr
80 and r1, r1, r0 @ clear bits outside the mask in the input
81 orr r2, r2, r1 @ set field
82 msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
84 mov sp, r3 @ restore stack pointer
85 ldmfd sp!, {r4-r12, lr} @ restore registers
86 bx lr @ return (hopefully thumb-safe!)
92 ASM_PFX(ArmReadCpacr):
93 mrc p15, 0, r0, c1, c0, 2
96 ASM_PFX(ArmWriteCpacr):
97 mcr p15, 0, r0, c1, c0, 2
101 ASM_PFX(ArmWriteAuxCr):
102 mcr p15, 0, r0, c1, c0, 1
105 ASM_PFX(ArmReadAuxCr):
106 mrc p15, 0, r0, c1, c0, 1
109 ASM_PFX(ArmSetTTBR0):
114 ASM_PFX(ArmGetTTBR0BaseAddress):
116 LoadConstantToReg(0xFFFFC000, r1)
123 //ArmUpdateTranslationTableEntry (
124 // IN VOID *TranslationTableEntry // R0
125 // IN VOID *MVA // R1
127 ASM_PFX(ArmUpdateTranslationTableEntry):
128 mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA
130 mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA
131 mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
136 ASM_PFX(ArmInvalidateTlb):
139 mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
145 mrc p15, 0, r0, c1, c1, 0
148 ASM_PFX(ArmWriteScr):
149 mcr p15, 0, r0, c1, c1, 0
152 ASM_PFX(ArmReadHVBar):
153 mrc p15, 4, r0, c12, c0, 0
156 ASM_PFX(ArmWriteHVBar):
157 mcr p15, 4, r0, c12, c0, 0
160 ASM_PFX(ArmReadMVBar):
161 mrc p15, 0, r0, c12, c0, 1
164 ASM_PFX(ArmWriteMVBar):
165 mcr p15, 0, r0, c12, c0, 1
176 ASM_PFX(ArmReadSctlr):
177 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
180 ASM_PFX(ArmReadCpuActlr):
181 mrc p15, 0, r0, c1, c0, 1
184 ASM_PFX(ArmWriteCpuActlr):
185 mcr p15, 0, r0, c1, c0, 1
190 ASM_FUNCTION_REMOVE_IF_UNREFERENCED