/** @file\r
\r
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
- Copyright (c) 2011-2013, ARM Ltd. All rights reserved.<BR>\r
+ Copyright (c) 2011-2014, ARM Ltd. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
// ARM Interrupt ID in Exception Table\r
#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ\r
\r
+// ID_PFR1 - ARM Processor Feature Register 1 definitions\r
+#define ARM_PFR1_SEC (0xFUL << 4)\r
+#define ARM_PFR1_TIMER (0xFUL << 16)\r
+#define ARM_PFR1_GIC (0xFUL << 28)\r
+\r
// Domain Access Control Register\r
#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))\r
#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))\r
\r
// MIDR - Main ID Register definitions\r
#define ARM_CPU_TYPE_MASK 0xFFF\r
+#define ARM_CPU_TYPE_AEMv8 0xD0F\r
+#define ARM_CPU_TYPE_A53 0xD03\r
+#define ARM_CPU_TYPE_A57 0xD07\r
#define ARM_CPU_TYPE_A15 0xC0F\r
#define ARM_CPU_TYPE_A9 0xC09\r
#define ARM_CPU_TYPE_A5 0xC05\r
\r
+#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )\r
+#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))\r
+\r
#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)\r
\r
VOID\r
VOID\r
);\r
\r
-UINTN \r
+UINTN\r
EFIAPI\r
ArmReadCbar (\r
VOID\r