// GICv3 specific registers\r
#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers\r
\r
-// the Affinity Routing Enable (ARE) bit in GICD_CTLR\r
-#define ARM_GIC_ICDDCR_ARE (1 << 4)\r
+// GICD_CTLR bits\r
+#define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE)\r
+#define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS)\r
\r
//\r
// GIC Redistributor\r