ArmPkg: update InvalidateInstructionCacheRange to flush only to PoU

[mirror_edk2.git] / ArmPkg / Include / Library / ArmGicLib.h

diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h
index 6cd93a1f54f64b7990546ee9a0fa3a12cd9812b3..10c4a9d72eb2f3d8612899851fbf34faf410d999 100644 (file)
--- a/ArmPkg/Include/Library/ArmGicLib.h
+++ b/ArmPkg/Include/Library/ArmGicLib.h
@@ -15,13 +15,7 @@
 #ifndef __ARMGIC_H\r
 #define __ARMGIC_H\r
 \r
-//\r
-// GIC definitions\r
-//\r
-typedef enum {\r
-  ARM_GIC_ARCH_REVISION_2,\r
-  ARM_GIC_ARCH_REVISION_3\r
-} ARM_GIC_ARCH_REVISION;\r
+#include <Library/ArmGicArchLib.h>\r
 \r
 //\r
 // GIC Distributor\r
@@ -53,6 +47,9 @@ typedef enum {
 // GICv3 specific registers\r
 #define ARM_GICD_IROUTER        0x6100 // Interrupt Routing Registers\r
 \r
+// the Affinity Routing Enable (ARE) bit in GICD_CTLR\r
+#define ARM_GIC_ICDDCR_ARE      (1 << 4)\r
+\r
 //\r
 // GIC Redistributor\r
 //\r
@@ -100,12 +97,6 @@ typedef enum {
 // Bit Mask for\r
 #define ARM_GIC_ICCIAR_ACKINTID                 0x3FF\r
 \r
-ARM_GIC_ARCH_REVISION\r
-EFIAPI\r
-ArmGicGetSupportedArchRevision (\r
-  VOID\r
-  );\r
-\r
 UINTN\r
 EFIAPI\r
 ArmGicGetInterfaceIdentification (\r
@@ -208,6 +199,7 @@ VOID
 EFIAPI\r
 ArmGicEnableInterrupt (\r
   IN UINTN                  GicDistributorBase,\r
+  IN UINTN                  GicRedistributorBase,\r
   IN UINTN                  Source\r
   );\r
 \r
@@ -215,6 +207,7 @@ VOID
 EFIAPI\r
 ArmGicDisableInterrupt (\r
   IN UINTN                  GicDistributorBase,\r
+  IN UINTN                  GicRedistributorBase,\r
   IN UINTN                  Source\r
   );\r
 \r
@@ -222,7 +215,102 @@ BOOLEAN
 EFIAPI\r
 ArmGicIsInterruptEnabled (\r
   IN UINTN                  GicDistributorBase,\r
+  IN UINTN                  GicRedistributorBase,\r
+  IN UINTN                  Source\r
+  );\r
+\r
+//\r
+// GIC revision 2 specific declarations\r
+//\r
+\r
+// Interrupts from 1020 to 1023 are considered as special interrupts (eg: spurious interrupts)\r
+#define ARM_GIC_IS_SPECIAL_INTERRUPTS(Interrupt) (((Interrupt) >= 1020) && ((Interrupt) <= 1023))\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV2SetupNonSecure (\r
+  IN  UINTN         MpId,\r
+  IN  INTN          GicDistributorBase,\r
+  IN  INTN          GicInterruptInterfaceBase\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV2EnableInterruptInterface (\r
+  IN  INTN          GicInterruptInterfaceBase\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV2DisableInterruptInterface (\r
+  IN  INTN          GicInterruptInterfaceBase\r
+  );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmGicV2AcknowledgeInterrupt (\r
+  IN  UINTN          GicInterruptInterfaceBase\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV2EndOfInterrupt (\r
+  IN UINTN                  GicInterruptInterfaceBase,\r
+  IN UINTN                  Source\r
+  );\r
+\r
+//\r
+// GIC revision 3 specific declarations\r
+//\r
+\r
+#define ICC_SRE_EL2_SRE         (1 << 0)\r
+\r
+#define ARM_GICD_IROUTER_IRM BIT31\r
+\r
+UINT32\r
+EFIAPI\r
+ArmGicV3GetControlSystemRegisterEnable (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV3SetControlSystemRegisterEnable (\r
+  IN UINT32         ControlSystemRegisterEnable\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV3EnableInterruptInterface (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV3DisableInterruptInterface (\r
+  VOID\r
+  );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmGicV3AcknowledgeInterrupt (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicV3EndOfInterrupt (\r
   IN UINTN                  Source\r
   );\r
 \r
+VOID\r
+ArmGicV3SetBinaryPointer (\r
+  IN UINTN                  BinaryPoint\r
+  );\r
+\r
+VOID\r
+ArmGicV3SetPriorityMask (\r
+  IN UINTN                  Priority\r
+  );\r
+\r
 #endif\r