/** @file\r
\r
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
- Copyright (c) 2011 - 2012, ARM Ltd. All rights reserved.<BR>\r
+ Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
\r
#include <Uefi/UefiBaseType.h>\r
\r
-#ifdef ARM_CPU_ARMv6\r
-#include <Chipset/ARM1176JZ-S.h>\r
+#ifdef MDE_CPU_ARM\r
+ #ifdef ARM_CPU_ARMv6\r
+ #include <Chipset/ARM1176JZ-S.h>\r
+ #else\r
+ #include <Chipset/ArmV7.h>\r
+ #endif\r
+#elif defined(MDE_CPU_AARCH64)\r
+ #include <Chipset/AArch64.h>\r
#else\r
-#include <Chipset/ArmV7.h>\r
+ #error "Unknown chipset."\r
#endif\r
\r
typedef enum {\r
typedef struct {\r
EFI_PHYSICAL_ADDRESS PhysicalBase;\r
EFI_VIRTUAL_ADDRESS VirtualBase;\r
- UINTN Length;\r
+ UINT64 Length;\r
ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r
} ARM_MEMORY_REGION_DESCRIPTOR;\r
\r
#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))\r
-// Get the position of the core for the Stack Offset (4 Core per Cluster)\r
-// Position = (ClusterId * 4) + CoreId\r
-#define GET_CORE_POS(MpId) ((((MpId) & ARM_CLUSTER_MASK) >> 6) + ((MpId) & ARM_CORE_MASK))\r
#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
\r
ARM_CACHE_TYPE\r
ArmDataCachePresent (\r
VOID\r
);\r
- \r
+\r
UINTN\r
EFIAPI\r
ArmDataCacheSize (\r
VOID\r
);\r
- \r
+\r
UINTN\r
EFIAPI\r
ArmDataCacheAssociativity (\r
VOID\r
);\r
- \r
+\r
UINTN\r
EFIAPI\r
ArmDataCacheLineLength (\r
VOID\r
);\r
- \r
+\r
BOOLEAN\r
EFIAPI\r
ArmInstructionCachePresent (\r
VOID\r
);\r
- \r
+\r
UINTN\r
EFIAPI\r
ArmInstructionCacheSize (\r
VOID\r
);\r
- \r
+\r
UINTN\r
EFIAPI\r
ArmInstructionCacheAssociativity (\r
VOID\r
);\r
- \r
+\r
UINTN\r
EFIAPI\r
ArmInstructionCacheLineLength (\r
VOID\r
);\r
- \r
-UINT32\r
+\r
+UINTN\r
EFIAPI\r
-Cp15IdCode (\r
+ArmIsArchTimerImplemented (\r
VOID\r
);\r
- \r
-UINT32\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadIdPfr0 (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadIdPfr1 (\r
+ VOID\r
+ );\r
+\r
+UINTN\r
EFIAPI\r
-Cp15CacheInfo (\r
+ArmCacheInfo (\r
VOID\r
);\r
\r
IN UINTN Address\r
);\r
\r
+VOID\r
+EFIAPI\r
+ArmInvalidateDataCacheEntryBySetWay (\r
+ IN UINTN SetWayFormat\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanDataCacheEntryBySetWay (\r
+ IN UINTN SetWayFormat\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanInvalidateDataCacheEntryBySetWay (\r
+ IN UINTN SetWayFormat\r
+ );\r
+\r
VOID\r
EFIAPI\r
ArmEnableDataCache (\r
ArmDisableInstructionCache (\r
VOID\r
);\r
- \r
+\r
VOID\r
EFIAPI\r
ArmEnableMmu (\r
\r
VOID\r
EFIAPI\r
-ArmDisableCachesAndMmu (\r
+ArmEnableCachesAndMmu (\r
VOID\r
);\r
\r
VOID\r
EFIAPI\r
-ArmInvalidateInstructionAndDataTlb (\r
+ArmDisableCachesAndMmu (\r
VOID\r
);\r
\r
VOID\r
);\r
\r
+VOID\r
+EFIAPI\r
+ArmEnableAsynchronousAbort (\r
+ VOID\r
+ );\r
+\r
UINTN\r
EFIAPI\r
-ArmDisableIrq (\r
+ArmDisableAsynchronousAbort (\r
VOID\r
);\r
\r
VOID\r
);\r
\r
+UINTN\r
+EFIAPI\r
+ArmDisableIrq (\r
+ VOID\r
+ );\r
+\r
VOID\r
EFIAPI\r
ArmEnableFiq (\r
ArmDisableFiq (\r
VOID\r
);\r
- \r
+\r
BOOLEAN\r
EFIAPI\r
ArmGetFiqState (\r
VOID\r
);\r
\r
+/**\r
+ * Invalidate Data and Instruction TLBs\r
+ */\r
VOID\r
EFIAPI\r
ArmInvalidateTlb (\r
VOID\r
);\r
- \r
+\r
VOID\r
EFIAPI\r
ArmUpdateTranslationTableEntry (\r
IN VOID *TranslationTableEntry,\r
IN VOID *Mva\r
);\r
- \r
+\r
VOID\r
EFIAPI\r
ArmSetDomainAccessControl (\r
VOID\r
);\r
\r
-VOID\r
+RETURN_STATUS\r
EFIAPI\r
ArmConfigureMmu (\r
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r
- OUT VOID **TranslationTableBase OPTIONAL,\r
+ OUT VOID **TranslationTableBase OPTIONAL,\r
OUT UINTN *TranslationTableSize OPTIONAL\r
);\r
- \r
+\r
BOOLEAN\r
EFIAPI\r
ArmMmuEnabled (\r
VOID\r
);\r
- \r
-VOID\r
-EFIAPI\r
-ArmSwitchProcessorMode (\r
- IN ARM_PROCESSOR_MODE Mode\r
- );\r
\r
-ARM_PROCESSOR_MODE\r
-EFIAPI\r
-ArmProcessorMode (\r
- VOID\r
- );\r
- \r
VOID\r
EFIAPI\r
ArmEnableBranchPrediction (\r
VOID\r
);\r
\r
+VOID\r
+EFIAPI\r
+ArmDrainWriteBuffer (\r
+ VOID\r
+ );\r
+\r
VOID\r
EFIAPI\r
ArmDataMemoryBarrier (\r
VOID\r
);\r
- \r
+\r
VOID\r
EFIAPI\r
ArmDataSyncronizationBarrier (\r
VOID\r
);\r
- \r
+\r
VOID\r
EFIAPI\r
ArmInstructionSynchronizationBarrier (\r
VOID\r
EFIAPI\r
ArmWriteVBar (\r
- IN UINT32 VectorBase\r
+ IN UINTN VectorBase\r
);\r
\r
-UINT32\r
+UINTN\r
EFIAPI\r
ArmReadVBar (\r
VOID\r
VOID\r
EFIAPI\r
ArmCallWFI (\r
+\r
VOID\r
);\r
\r
VOID\r
);\r
\r
+UINTN\r
+EFIAPI\r
+ArmReadMidr (\r
+ VOID\r
+ );\r
+\r
UINT32\r
EFIAPI\r
ArmReadCpacr (\r
VOID\r
);\r
\r
-UINT32\r
-EFIAPI\r
-ArmReadNsacr (\r
- VOID\r
- );\r
+/**\r
+ Get the Secure Configuration Register value\r
\r
-VOID\r
-EFIAPI\r
-ArmWriteNsacr (\r
- IN UINT32 SetWayFormat\r
- );\r
+ @return Value read from the Secure Configuration Register\r
\r
+**/\r
UINT32\r
EFIAPI\r
ArmReadScr (\r
VOID\r
);\r
\r
+/**\r
+ Set the Secure Configuration Register\r
+\r
+ @param Value Value to write to the Secure Configuration Register\r
+\r
+**/\r
VOID\r
EFIAPI\r
ArmWriteScr (\r
- IN UINT32 SetWayFormat\r
+ IN UINT32 Value\r
);\r
\r
UINT32\r
IN UINTN HypModeVectorBase\r
);\r
\r
+\r
+//\r
+// Helper functions for accessing CPU ACTLR\r
+//\r
+\r
+UINTN\r
+EFIAPI\r
+ArmReadCpuActlr (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmWriteCpuActlr (\r
+ IN UINTN Val\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmSetCpuActlrBit (\r
+ IN UINTN Bits\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmUnsetCpuActlrBit (\r
+ IN UINTN Bits\r
+ );\r
+\r
#endif // __ARM_LIB__\r