ArmPkg: Move cache defs used in Universal/Smbios into ArmCache.h

[mirror_edk2.git] / ArmPkg / Include / Library / ArmLib.h

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 5c232d779c833e54a5dac5d51e9e5cb49e85f250..79ea755777a9a6f2cb042794f552ed38d63f631a 100644 (file)
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -2,7 +2,7 @@
 \r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
   Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
-  Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>\r
+  Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>\r
 \r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
@@ -109,9 +109,37 @@ typedef enum {
 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))\r
 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
 \r
-// The ARM Architecture Reference Manual for ARMv8-A defines up\r
-// to 7 levels of cache, L1 through L7.\r
-#define MAX_ARM_CACHE_LEVEL   7\r
+/** Reads the CCSIDR register for the specified cache.\r
+\r
+  @param CSSELR The CSSELR cache selection register value.\r
+\r
+  @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.\r
+          Returns the contents of the CCSIDR register in AARCH32 mode.\r
+**/\r
+UINTN\r
+ReadCCSIDR (\r
+  IN UINT32 CSSELR\r
+  );\r
+\r
+/** Reads the CCSIDR2 for the specified cache.\r
+\r
+  @param CSSELR The CSSELR cache selection register value\r
+\r
+  @return The contents of the CCSIDR2 register for the specified cache.\r
+**/\r
+UINT32\r
+ReadCCSIDR2 (\r
+  IN UINT32 CSSELR\r
+  );\r
+\r
+/** Reads the Cache Level ID (CLIDR) register.\r
+\r
+  @return The contents of the CLIDR_EL1 register.\r
+**/\r
+UINT32\r
+ReadCLIDR (\r
+  VOID\r
+  );\r
 \r
 UINTN\r
 EFIAPI\r