ArmPkg: Move cache defs used in Universal/Smbios into ArmCache.h

Many of the cache definitions in ArmLibPrivate.h are being used outside
of ArmLib, in Universal/Smbios. Move them into ArmCache.h to make them
public, and remove the include of ArmLibPrivate.h from files in
Universal/Smbios.

Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>

diff --git a/ArmPkg/Include/IndustryStandard/ArmCache.h b/ArmPkg/Include/IndustryStandard/ArmCache.h
new file mode 100644 (file)
index 0000000..f9de46b
--- /dev/null
+++ b/ArmPkg/Include/IndustryStandard/ArmCache.h
@@ -0,0 +1,112 @@
+/** @file\r
+\r
+  Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>\r
+\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#ifndef ARM_CACHE_H_\r
+#define ARM_CACHE_H_\r
+\r
+#include <Uefi/UefiBaseType.h>\r
+\r
+// The ARM Architecture Reference Manual for ARMv8-A defines up\r
+// to 7 levels of cache, L1 through L7.\r
+#define MAX_ARM_CACHE_LEVEL   7\r
+\r
+/// Defines the structure of the CSSELR (Cache Size Selection) register\r
+typedef union {\r
+  struct {\r
+    UINT32    InD       :1;  ///< Instruction not Data bit\r
+    UINT32    Level     :3;  ///< Cache level (zero based)\r
+    UINT32    TnD       :1;  ///< Allocation not Data bit\r
+    UINT32    Reserved  :27; ///< Reserved, RES0\r
+  } Bits; ///< Bitfield definition of the register\r
+  UINT32 Data; ///< The entire 32-bit value\r
+} CSSELR_DATA;\r
+\r
+/// The cache type values for the InD field of the CSSELR register\r
+typedef enum\r
+{\r
+  /// Select the data or unified cache\r
+  CsselrCacheTypeDataOrUnified = 0,\r
+  /// Select the instruction cache\r
+  CsselrCacheTypeInstruction,\r
+  CsselrCacheTypeMax\r
+} CSSELR_CACHE_TYPE;\r
+\r
+/// Defines the structure of the CCSIDR (Current Cache Size ID) register\r
+typedef union {\r
+  struct {\r
+    UINT64    LineSize           :3;  ///< Line size (Log2(Num bytes in cache) - 4)\r
+    UINT64    Associativity      :10; ///< Associativity - 1\r
+    UINT64    NumSets            :15; ///< Number of sets in the cache -1\r
+    UINT64    Unknown            :4;  ///< Reserved, UNKNOWN\r
+    UINT64    Reserved           :32; ///< Reserved, RES0\r
+  } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.\r
+  struct {\r
+    UINT64    LineSize           :3;  ///< Line size (Log2(Num bytes in cache) - 4)\r
+    UINT64    Associativity      :21; ///< Associativity - 1\r
+    UINT64    Reserved1          :8;  ///< Reserved, RES0\r
+    UINT64    NumSets            :24; ///< Number of sets in the cache -1\r
+    UINT64    Reserved2          :8;  ///< Reserved, RES0\r
+  } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.\r
+  struct {\r
+    UINT64    LineSize           : 3;\r
+    UINT64    Associativity      : 21;\r
+    UINT64    Reserved           : 8;\r
+    UINT64    Unallocated        : 32;\r
+  } BitsCcidxAA32;\r
+  UINT64 Data; ///< The entire 64-bit value\r
+} CCSIDR_DATA;\r
+\r
+/// Defines the structure of the AARCH32 CCSIDR2 register.\r
+typedef union {\r
+  struct {\r
+    UINT32 NumSets               :24; ///< Number of sets in the cache - 1\r
+    UINT32 Reserved              :8;  ///< Reserved, RES0\r
+  } Bits; ///< Bitfield definition of the register\r
+  UINT32 Data; ///< The entire 32-bit value\r
+} CCSIDR2_DATA;\r
+\r
+/** Defines the structure of the CLIDR (Cache Level ID) register.\r
+ *\r
+ * The lower 32 bits are the same for both AARCH32 and AARCH64\r
+ * so we can use the same structure for both.\r
+**/\r
+typedef union {\r
+  struct {\r
+    UINT32    Ctype1   : 3; ///< Level 1 cache type\r
+    UINT32    Ctype2   : 3; ///< Level 2 cache type\r
+    UINT32    Ctype3   : 3; ///< Level 3 cache type\r
+    UINT32    Ctype4   : 3; ///< Level 4 cache type\r
+    UINT32    Ctype5   : 3; ///< Level 5 cache type\r
+    UINT32    Ctype6   : 3; ///< Level 6 cache type\r
+    UINT32    Ctype7   : 3; ///< Level 7 cache type\r
+    UINT32    LoUIS    : 3; ///< Level of Unification Inner Shareable\r
+    UINT32    LoC      : 3; ///< Level of Coherency\r
+    UINT32    LoUU     : 3; ///< Level of Unification Uniprocessor\r
+    UINT32    Icb      : 3; ///< Inner Cache Boundary\r
+  } Bits; ///< Bitfield definition of the register\r
+  UINT32 Data; ///< The entire 32-bit value\r
+} CLIDR_DATA;\r
+\r
+/// The cache types reported in the CLIDR register.\r
+typedef enum {\r
+  /// No cache is present\r
+  ClidrCacheTypeNone = 0,\r
+  /// There is only an instruction cache\r
+  ClidrCacheTypeInstructionOnly,\r
+  /// There is only a data cache\r
+  ClidrCacheTypeDataOnly,\r
+  /// There are separate data and instruction caches\r
+  ClidrCacheTypeSeparate,\r
+  /// There is a unified cache\r
+  ClidrCacheTypeUnified,\r
+  ClidrCacheTypeMax\r
+} CLIDR_CACHE_TYPE;\r
+\r
+#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)\r
+\r
+#endif /* ARM_CACHE_H_ */\r

diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h
index 5c232d779c833e54a5dac5d51e9e5cb49e85f250..79ea755777a9a6f2cb042794f552ed38d63f631a 100644 (file)
--- a/ArmPkg/Include/Library/ArmLib.h
+++ b/ArmPkg/Include/Library/ArmLib.h
@@ -2,7 +2,7 @@
 \r
   Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
   Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
-  Copyright (c) 2020, NUVIA Inc. All rights reserved.<BR>\r
+  Copyright (c) 2020 - 2021, NUVIA Inc. All rights reserved.<BR>\r
 \r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
@@ -109,9 +109,37 @@ typedef enum {
 #define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))\r
 #define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
 \r
-// The ARM Architecture Reference Manual for ARMv8-A defines up\r
-// to 7 levels of cache, L1 through L7.\r
-#define MAX_ARM_CACHE_LEVEL   7\r
+/** Reads the CCSIDR register for the specified cache.\r
+\r
+  @param CSSELR The CSSELR cache selection register value.\r
+\r
+  @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.\r
+          Returns the contents of the CCSIDR register in AARCH32 mode.\r
+**/\r
+UINTN\r
+ReadCCSIDR (\r
+  IN UINT32 CSSELR\r
+  );\r
+\r
+/** Reads the CCSIDR2 for the specified cache.\r
+\r
+  @param CSSELR The CSSELR cache selection register value\r
+\r
+  @return The contents of the CCSIDR2 register for the specified cache.\r
+**/\r
+UINT32\r
+ReadCCSIDR2 (\r
+  IN UINT32 CSSELR\r
+  );\r
+\r
+/** Reads the Cache Level ID (CLIDR) register.\r
+\r
+  @return The contents of the CLIDR_EL1 register.\r
+**/\r
+UINT32\r
+ReadCLIDR (\r
+  VOID\r
+  );\r
 \r
 UINTN\r
 EFIAPI\r

diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/ArmLibPrivate.h
index 5db83d620bfce8bf4b6b7834a84ad43014a7fd59..668aefd6a08878a45ae5e8e5b402f49f211ab526 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h
+++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h
@@ -52,101 +52,6 @@
 #define CACHE_ARCHITECTURE_UNIFIED            (0UL)\r
 #define CACHE_ARCHITECTURE_SEPARATE           (1UL)\r
 \r
-\r
-/// Defines the structure of the CSSELR (Cache Size Selection) register\r
-typedef union {\r
-  struct {\r
-    UINT32    InD       :1;  ///< Instruction not Data bit\r
-    UINT32    Level     :3;  ///< Cache level (zero based)\r
-    UINT32    TnD       :1;  ///< Allocation not Data bit\r
-    UINT32    Reserved  :27; ///< Reserved, RES0\r
-  } Bits; ///< Bitfield definition of the register\r
-  UINT32 Data; ///< The entire 32-bit value\r
-} CSSELR_DATA;\r
-\r
-/// The cache type values for the InD field of the CSSELR register\r
-typedef enum\r
-{\r
-  /// Select the data or unified cache\r
-  CsselrCacheTypeDataOrUnified = 0,\r
-  /// Select the instruction cache\r
-  CsselrCacheTypeInstruction,\r
-  CsselrCacheTypeMax\r
-} CSSELR_CACHE_TYPE;\r
-\r
-/// Defines the structure of the CCSIDR (Current Cache Size ID) register\r
-typedef union {\r
-  struct {\r
-    UINT64    LineSize           :3;  ///< Line size (Log2(Num bytes in cache) - 4)\r
-    UINT64    Associativity      :10; ///< Associativity - 1\r
-    UINT64    NumSets            :15; ///< Number of sets in the cache -1\r
-    UINT64    Unknown            :4;  ///< Reserved, UNKNOWN\r
-    UINT64    Reserved           :32; ///< Reserved, RES0\r
-  } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.\r
-  struct {\r
-    UINT64    LineSize           :3;  ///< Line size (Log2(Num bytes in cache) - 4)\r
-    UINT64    Associativity      :21; ///< Associativity - 1\r
-    UINT64    Reserved1          :8;  ///< Reserved, RES0\r
-    UINT64    NumSets            :24; ///< Number of sets in the cache -1\r
-    UINT64    Reserved2          :8;  ///< Reserved, RES0\r
-  } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.\r
-  struct {\r
-    UINT64    LineSize           : 3;\r
-    UINT64    Associativity      : 21;\r
-    UINT64    Reserved           : 8;\r
-    UINT64    Unallocated        : 32;\r
-  } BitsCcidxAA32;\r
-  UINT64 Data; ///< The entire 64-bit value\r
-} CCSIDR_DATA;\r
-\r
-/// Defines the structure of the AARCH32 CCSIDR2 register.\r
-typedef union {\r
-  struct {\r
-    UINT32 NumSets               :24; ///< Number of sets in the cache - 1\r
-    UINT32 Reserved              :8;  ///< Reserved, RES0\r
-  } Bits; ///< Bitfield definition of the register\r
-  UINT32 Data; ///< The entire 32-bit value\r
-} CCSIDR2_DATA;\r
-\r
-/** Defines the structure of the CLIDR (Cache Level ID) register.\r
- *\r
- * The lower 32 bits are the same for both AARCH32 and AARCH64\r
- * so we can use the same structure for both.\r
-**/\r
-typedef union {\r
-  struct {\r
-    UINT32    Ctype1   : 3; ///< Level 1 cache type\r
-    UINT32    Ctype2   : 3; ///< Level 2 cache type\r
-    UINT32    Ctype3   : 3; ///< Level 3 cache type\r
-    UINT32    Ctype4   : 3; ///< Level 4 cache type\r
-    UINT32    Ctype5   : 3; ///< Level 5 cache type\r
-    UINT32    Ctype6   : 3; ///< Level 6 cache type\r
-    UINT32    Ctype7   : 3; ///< Level 7 cache type\r
-    UINT32    LoUIS    : 3; ///< Level of Unification Inner Shareable\r
-    UINT32    LoC      : 3; ///< Level of Coherency\r
-    UINT32    LoUU     : 3; ///< Level of Unification Uniprocessor\r
-    UINT32    Icb      : 3; ///< Inner Cache Boundary\r
-  } Bits; ///< Bitfield definition of the register\r
-  UINT32 Data; ///< The entire 32-bit value\r
-} CLIDR_DATA;\r
-\r
-/// The cache types reported in the CLIDR register.\r
-typedef enum {\r
-  /// No cache is present\r
-  ClidrCacheTypeNone = 0,\r
-  /// There is only an instruction cache\r
-  ClidrCacheTypeInstructionOnly,\r
-  /// There is only a data cache\r
-  ClidrCacheTypeDataOnly,\r
-  /// There are separate data and instruction caches\r
-  ClidrCacheTypeSeparate,\r
-  /// There is a unified cache\r
-  ClidrCacheTypeUnified,\r
-  ClidrCacheTypeMax\r
-} CLIDR_CACHE_TYPE;\r
-\r
-#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)\r
-\r
 VOID\r
 CPSRMaskInsert (\r
   IN  UINT32  Mask,\r
@@ -158,32 +63,4 @@ CPSRRead (
   VOID\r
   );\r
 \r
-/** Reads the CCSIDR register for the specified cache.\r
-\r
-  @param CSSELR The CSSELR cache selection register value.\r
-\r
-  @return The contents of the CCSIDR_EL1 register for the specified cache, when in AARCH64 mode.\r
-          Returns the contents of the CCSIDR register in AARCH32 mode.\r
-**/\r
-UINTN\r
-ReadCCSIDR (\r
-  IN UINT32 CSSELR\r
-  );\r
-\r
-/** Reads the CCSIDR2 for the specified cache.\r
-\r
-  @param CSSELR The CSSELR cache selection register value\r
-\r
-  @return The contents of the CCSIDR2 register for the specified cache.\r
-**/\r
-UINT32\r
-ReadCCSIDR2 (\r
-  IN UINT32 CSSELR\r
-  );\r
-\r
-UINT32\r
-ReadCLIDR (\r
-  VOID\r
-  );\r
-\r
 #endif // ARM_LIB_PRIVATE_H_\r

diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
index 0cb56c53975e9ba4b0a6dc0d8f2add163a0ee1cb..fb484086a4570b1765782fe7b8dc81f4d106eda2 100644 (file)
--- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
+++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c
@@ -10,11 +10,11 @@
 \r
 #include <Uefi.h>\r
 #include <Protocol/Smbios.h>\r
+#include <IndustryStandard/ArmCache.h>\r
 #include <IndustryStandard/ArmStdSmc.h>\r
 #include <IndustryStandard/SmBios.h>\r
 #include <Library/ArmLib.h>\r
 #include <Library/ArmSmcLib.h>\r
-#include <Library/ArmLib/ArmLibPrivate.h>\r
 #include <Library/BaseLib.h>\r
 #include <Library/BaseMemoryLib.h>\r
 #include <Library/DebugLib.h>\r

diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c
index ddd774b16f83ad124050897291b64cf13c9a5e83..6fbb95afb21505c36865a08afd0eca42f2fb5c88 100644 (file)
--- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c
+++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c
@@ -8,8 +8,8 @@
 **/\r
 \r
 #include <Uefi.h>\r
+#include <IndustryStandard/ArmCache.h>\r
 #include <Library/ArmLib.h>\r
-#include <Library/ArmLib/ArmLibPrivate.h>\r
 \r
 #include "SmbiosProcessor.h"\r
 \r

diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c
index c78bd41a7e060d090148c7ca4ea971cc019b59c0..7616fca425fd8cd0c515e332d797041fa13f63a8 100644 (file)
--- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c
+++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c
@@ -8,8 +8,8 @@
 **/\r
 \r
 #include <Uefi.h>\r
+#include <IndustryStandard/ArmCache.h>\r
 #include <Library/ArmLib.h>\r
-#include <Library/ArmLib/ArmLibPrivate.h>\r
 \r
 #include "SmbiosProcessor.h"\r
 \r

diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c
index bccb21cfbb41849fa9e714f95f0d9fee18333408..292f10bf97ebe964fb05e4d4d894d9fdcc057250 100644 (file)
--- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c
+++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c
@@ -8,10 +8,10 @@
 **/\r
 \r
 #include <Uefi.h>\r
+#include <IndustryStandard/ArmCache.h>\r
 #include <IndustryStandard/ArmStdSmc.h>\r
 #include <IndustryStandard/SmBios.h>\r
 #include <Library/ArmLib.h>\r
-#include <Library/ArmLib/ArmLibPrivate.h>\r
 #include <Library/ArmSmcLib.h>\r
 #include <Library/BaseMemoryLib.h>\r
 \r