ArmPkg: CpuDxe: fix AArch64 interrupt read masks

[mirror_edk2.git] / ArmPkg / Library / ArmLib / AArch64 / AArch64Mmu.c

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
index e40c09ae9685cdc8416b2e345a4e89f115a4dc00..f967a6478840c99aaa4401b7ec99ac67eb1bb801 100644 (file)
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
@@ -34,24 +34,26 @@ ArmMemoryAttributeToPageAttribute (
 {\r
   switch (Attributes) {\r
   case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r
-    return TT_ATTR_INDX_MEMORY_WRITE_BACK;\r
-  case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
-    return TT_ATTR_INDX_MEMORY_WRITE_THROUGH;\r
-  case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:\r
-    return TT_ATTR_INDX_DEVICE_MEMORY;\r
-  case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r
-    return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;\r
   case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
-    return TT_ATTR_INDX_MEMORY_WRITE_BACK;\r
+    return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;\r
+\r
+  case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
   case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r
-    return TT_ATTR_INDX_MEMORY_WRITE_THROUGH;\r
-  case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:\r
-    return TT_ATTR_INDX_DEVICE_MEMORY;\r
+    return TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;\r
+\r
+  // Uncached and device mappings are treated as outer shareable by default,\r
+  case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r
   case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r
     return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;\r
+\r
   default:\r
     ASSERT(0);\r
-    return TT_ATTR_INDX_DEVICE_MEMORY;\r
+  case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:\r
+  case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:\r
+    if (ArmReadCurrentEL () == AARCH64_EL2)\r
+      return TT_ATTR_INDX_DEVICE_MEMORY | TT_TABLE_XN;\r
+    else\r
+      return TT_ATTR_INDX_DEVICE_MEMORY | TT_TABLE_UXN | TT_TABLE_PXN;\r
   }\r
 }\r
 \r
@@ -97,48 +99,6 @@ PageAttributeToGcdAttribute (
   return GcdAttributes;\r
 }\r
 \r
-UINT64\r
-GcdAttributeToPageAttribute (\r
-  IN UINT64 GcdAttributes\r
-  )\r
-{\r
-  UINT64  PageAttributes;\r
-\r
-  switch (GcdAttributes & 0xFF) {\r
-  case EFI_MEMORY_UC:\r
-    PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;\r
-    break;\r
-  case EFI_MEMORY_WC:\r
-    PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;\r
-    break;\r
-  case EFI_MEMORY_WT:\r
-    PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH;\r
-    break;\r
-  case EFI_MEMORY_WB:\r
-    PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK;\r
-    break;\r
-  default:\r
-    DEBUG ((EFI_D_ERROR, "GcdAttributeToPageAttribute: 0x%X attributes is not supported.\n", GcdAttributes));\r
-    ASSERT (0);\r
-    // If no match has been found then we mark the memory as device memory.\r
-    // The only side effect of using device memory should be a slow down in the performance.\r
-    PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;\r
-  }\r
-\r
-  // Determine protection attributes\r
-  if (GcdAttributes & EFI_MEMORY_WP) {\r
-    // Read only cases map to write-protect\r
-    PageAttributes |= TT_AP_RO_RO;\r
-  }\r
-\r
-  // Process eXecute Never attribute\r
-  if (GcdAttributes & EFI_MEMORY_XP) {\r
-    PageAttributes |= (TT_PXN_MASK | TT_UXN_MASK);\r
-  }\r
-\r
-  return PageAttributes;\r
-}\r
-\r
 ARM_MEMORY_REGION_ATTRIBUTES\r
 GcdAttributeToArmAttribute (\r
   IN UINT64 GcdAttributes\r
@@ -668,7 +628,8 @@ ArmConfigureMmu (
       return RETURN_UNSUPPORTED;\r
     }\r
   } else if (ArmReadCurrentEL () == AARCH64_EL1) {\r
-    TCR = T0SZ | TCR_TG0_4KB;\r
+    // Due to Cortex-A57 erratum #822227 we must set TG1[1] == 1, regardless of EPD1.\r
+    TCR = T0SZ | TCR_TG0_4KB | TCR_TG1_4KB | TCR_EPD1;\r
 \r
     // Set the Physical Address Size using MaxAddress\r
     if (MaxAddress < SIZE_4GB) {\r