#------------------------------------------------------------------------------\r
#\r
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-# Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.\r
+# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)\r
GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)\r
GCC_ASM_EXPORT (ArmWriteVBar)\r
-GCC_ASM_EXPORT (ArmVFPImplemented)\r
+GCC_ASM_EXPORT (ArmReadVBar)\r
GCC_ASM_EXPORT (ArmEnableVFP)\r
GCC_ASM_EXPORT (ArmCallWFI)\r
-GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)\r
GCC_ASM_EXPORT (ArmReadMpidr)\r
GCC_ASM_EXPORT (ArmReadTpidrurw)\r
GCC_ASM_EXPORT (ArmWriteTpidrurw)\r
2: mrs x0, sctlr_el2 // Read System Control Register EL2\r
b 4f\r
3: mrs x0, sctlr_el3 // Read System Control Register EL3\r
-4: bic x0, x0, #CTRL_M_BIT // Clear MMU enable bit\r
+4: and x0, x0, #~CTRL_M_BIT // Clear MMU enable bit\r
EL1_OR_EL2_OR_EL3(x1)\r
1: msr sctlr_el1, x0 // Write back\r
tlbi vmalle1\r
2: mrs x0, sctlr_el2 // Get control register EL2\r
b 4f\r
3: mrs x0, sctlr_el3 // Get control register EL3\r
-4: bic x0, x0, #CTRL_M_BIT // Disable MMU\r
- bic x0, x0, #CTRL_C_BIT // Disable D Cache\r
- bic x0, x0, #CTRL_I_BIT // Disable I Cache\r
+4: mov x1, #~(CTRL_M_BIT | CTRL_C_BIT | CTRL_I_BIT) // Disable MMU, D & I caches\r
+ and x0, x0, x1\r
EL1_OR_EL2_OR_EL3(x1)\r
1: msr sctlr_el1, x0 // Write back control register\r
b 4f\r
2: mrs x0, sctlr_el2 // Get control register EL2\r
b 4f\r
3: mrs x0, sctlr_el3 // Get control register EL3\r
-4: bic x0, x0, #CTRL_C_BIT // Clear C bit\r
+4: and x0, x0, #~CTRL_C_BIT // Clear C bit\r
EL1_OR_EL2_OR_EL3(x1)\r
1: msr sctlr_el1, x0 // Write back control register\r
b 4f\r
2: mrs x0, sctlr_el2 // Get control register EL2\r
b 4f\r
3: mrs x0, sctlr_el3 // Get control register EL3\r
-4: bic x0, x0, #CTRL_I_BIT // Clear I bit\r
+4: and x0, x0, #~CTRL_I_BIT // Clear I bit\r
EL1_OR_EL2_OR_EL3(x1)\r
1: msr sctlr_el1, x0 // Write back control register\r
b 4f\r
2: mrs x0, sctlr_el2 // Get control register EL2\r
b 4f\r
3: mrs x0, sctlr_el3 // Get control register EL3\r
-4: bic x0, x0, #CTRL_A_BIT // Clear A (alignment check) bit\r
+4: and x0, x0, #~CTRL_A_BIT // Clear A (alignment check) bit\r
EL1_OR_EL2_OR_EL3(x1)\r
1: msr sctlr_el1, x0 // Write back control register\r
b 4f\r
\r
ASM_PFX(AArch64AllDataCachesOperation):\r
// We can use regs 0-7 and 9-15 without having to save/restore.\r
-// Save our link register on the stack.\r
- str x30, [sp, #-0x10]!\r
+// Save our link register on the stack. - The stack must always be quad-word aligned\r
+ str x30, [sp, #-16]!\r
mov x1, x0 // Save Function call in x1\r
mrs x6, clidr_el1 // Read EL1 CLIDR\r
and x3, x6, #0x7000000 // Mask out all but Level of Coherency (LoC)\r
\r
ASM_PFX(AArch64PerformPoUDataCacheOperation):\r
// We can use regs 0-7 and 9-15 without having to save/restore.\r
-// Save our link register on the stack.\r
- str x30, [sp, #-0x10]!\r
+// Save our link register on the stack. - The stack must always be quad-word aligned\r
+ str x30, [sp, #-16]!\r
mov x1, x0 // Save Function call in x1\r
mrs x6, clidr_el1 // Read EL1 CLIDR\r
and x3, x6, #0x38000000 // Mask out all but Point of Unification (PoU)\r
4: isb\r
ret\r
\r
+ASM_PFX(ArmReadVBar):\r
+ EL1_OR_EL2_OR_EL3(x1)\r
+1: mrs x0, vbar_el1 // Set the Address of the EL1 Vector Table in the VBAR register\r
+ ret\r
+2: mrs x0, vbar_el2 // Set the Address of the EL2 Vector Table in the VBAR register\r
+ ret\r
+3: mrs x0, vbar_el3 // Set the Address of the EL3 Vector Table in the VBAR register\r
+ ret\r
+\r
+\r
ASM_PFX(ArmEnableVFP):\r
// Check whether floating-point is implemented in the processor.\r
mov x1, x30 // Save LR\r
ret\r
\r
\r
-ASM_PFX(ArmInvalidateInstructionAndDataTlb):\r
- EL1_OR_EL2_OR_EL3(x0)\r
-1: tlbi vmalle1\r
- b 4f\r
-2: tlbi alle2\r
- b 4f\r
-3: tlbi alle3\r
-4: dsb sy\r
- isb\r
- ret\r
-\r
-\r
ASM_PFX(ArmReadMpidr):\r
mrs x0, mpidr_el1 // read EL1 MPIDR\r
ret\r
mrs x0, CurrentEL\r
ret\r
\r
-dead:\r
- b dead\r
-\r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r