ArmPkg: Ensured the stack is always quad-word aligned

From the AArch64 Procedure Call Standard (ARM IHI 0055B):

  5.2.2.1 Universal stack constraints
  At all times the following basic constraints must hold:
  - SP mod 16 = 0. The stack must be quad-word aligned.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@16327 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Library/ArmHvcLib/AArch64/ArmHvc.S b/ArmPkg/Library/ArmHvcLib/AArch64/ArmHvc.S
index a15ae03e0f25ab916a423ae7688314494753521c..99a1d21ce7f18f8e3fcf38cf4ac3e85f11d619d2 100644 (file)
--- a/ArmPkg/Library/ArmHvcLib/AArch64/ArmHvc.S
+++ b/ArmPkg/Library/ArmHvcLib/AArch64/ArmHvc.S
@@ -18,8 +18,8 @@
 GCC_ASM_EXPORT(ArmCallHvc)\r
 \r
 ASM_PFX(ArmCallHvc):\r
-  // Push x0 on the stack\r
-  str   x0, [sp, #-8]!\r
+  // Push x0 on the stack - The stack must always be quad-word aligned\r
+  str   x0, [sp, #-16]!\r
 \r
   // Load the HVC arguments values into the appropriate registers\r
   ldp   x6, x7, [x0, #48]\r
@@ -30,9 +30,9 @@ ASM_PFX(ArmCallHvc):
   hvc   #0\r
 \r
   // Pop the ARM_HVC_ARGS structure address from the stack into x9\r
-  ldr   x9, [sp], #8\r
+  ldr   x9, [sp], #16\r
 \r
-  // Store the HVC returned values into the appropriate registers\r
+  // Store the HVC returned values into the ARM_HVC_ARGS structure.\r
   // A HVC call can return up to 4 values\r
   stp   x2, x3, [x9, #16]\r
   stp   x0, x1, [x9, #0]\r

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
index 98eba3cac25ee6bbdc0e1ac93a76d6b51a9fc7b4..bdede48724e62c2759ca56d442ebb05acac22dcb 100644 (file)
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
@@ -313,8 +313,8 @@ ASM_PFX(ArmDisableBranchPrediction):
 \r
 ASM_PFX(AArch64AllDataCachesOperation):\r
 // We can use regs 0-7 and 9-15 without having to save/restore.\r
-// Save our link register on the stack.\r
-  str   x30, [sp, #-0x10]!\r
+// Save our link register on the stack. - The stack must always be quad-word aligned\r
+  str   x30, [sp, #-16]!\r
   mov   x1, x0                  // Save Function call in x1\r
   mrs   x6, clidr_el1           // Read EL1 CLIDR\r
   and   x3, x6, #0x7000000      // Mask out all but Level of Coherency (LoC)\r
@@ -326,8 +326,8 @@ ASM_PFX(AArch64AllDataCachesOperation):
 \r
 ASM_PFX(AArch64PerformPoUDataCacheOperation):\r
 // We can use regs 0-7 and 9-15 without having to save/restore.\r
-// Save our link register on the stack.\r
-  str   x30, [sp, #-0x10]!\r
+// Save our link register on the stack. - The stack must always be quad-word aligned\r
+  str   x30, [sp, #-16]!\r
   mov   x1, x0                  // Save Function call in x1\r
   mrs   x6, clidr_el1           // Read EL1 CLIDR\r
   and   x3, x6, #0x38000000     // Mask out all but Point of Unification (PoU)\r

diff --git a/ArmPkg/Library/ArmSmcLib/AArch64/ArmSmc.S b/ArmPkg/Library/ArmSmcLib/AArch64/ArmSmc.S
index f73c98cfc38bde9c88f590ccd04e82f275c240b5..46c17674c199aae7fc94a0d62539b76bb6f41ac7 100644 (file)
--- a/ArmPkg/Library/ArmSmcLib/AArch64/ArmSmc.S
+++ b/ArmPkg/Library/ArmSmcLib/AArch64/ArmSmc.S
@@ -17,8 +17,8 @@
 GCC_ASM_EXPORT(ArmCallSmc)\r
 \r
 ASM_PFX(ArmCallSmc):\r
-  // Push x0 on the stack\r
-  str   x0, [sp, #-8]!\r
+  // Push x0 on the stack - The stack must always be quad-word aligned\r
+  str   x0, [sp, #-16]!\r
 \r
   // Load the SMC arguments values into the appropriate registers\r
   ldp   x6, x7, [x0, #48]\r
@@ -29,9 +29,9 @@ ASM_PFX(ArmCallSmc):
   smc   #0\r
 \r
   // Pop the ARM_SMC_ARGS structure address from the stack into x9\r
-  ldr   x9, [sp], #8\r
+  ldr   x9, [sp], #16\r
 \r
-  // Store the SMC returned values into the appropriate registers\r
+  // Store the SMC returned values into the ARM_SMC_ARGS structure.\r
   // A SMC call can return up to 4 values - we do not need to store back x4-x7.\r
   stp   x2, x3, [x9, #16]\r
   stp   x0, x1, [x9, #0]\r