\r
.set MPIDR_U_BIT, (30)\r
.set MPIDR_U_MASK, (1 << MPIDR_U_BIT)\r
-.set DAIF_FIQ_BIT, (1 << 0)\r
-.set DAIF_IRQ_BIT, (1 << 1)\r
-.set DAIF_ABORT_BIT, (1 << 2)\r
-.set DAIF_DEBUG_BIT, (1 << 3)\r
-.set DAIF_INT_BITS, (DAIF_FIQ_BIT | DAIF_IRQ_BIT)\r
-.set DAIF_ALL, (DAIF_DEBUG_BIT | DAIF_ABORT_BIT | DAIF_INT_BITS)\r
+\r
+// DAIF bit definitions for writing through msr daifclr/sr daifset\r
+.set DAIF_WR_FIQ_BIT, (1 << 0)\r
+.set DAIF_WR_IRQ_BIT, (1 << 1)\r
+.set DAIF_WR_ABORT_BIT, (1 << 2)\r
+.set DAIF_WR_DEBUG_BIT, (1 << 3)\r
+.set DAIF_WR_INT_BITS, (DAIF_WR_FIQ_BIT | DAIF_WR_IRQ_BIT)\r
+.set DAIF_WR_ALL, (DAIF_WR_DEBUG_BIT | DAIF_WR_ABORT_BIT | DAIF_WR_INT_BITS)\r
\r
\r
ASM_PFX(ArmIsMpCore):\r
\r
\r
ASM_PFX(ArmEnableAsynchronousAbort):\r
- msr daifclr, #DAIF_ABORT_BIT\r
+ msr daifclr, #DAIF_WR_ABORT_BIT\r
isb\r
ret\r
\r
\r
ASM_PFX(ArmDisableAsynchronousAbort):\r
- msr daifset, #DAIF_ABORT_BIT\r
+ msr daifset, #DAIF_WR_ABORT_BIT\r
isb\r
ret\r
\r
\r
ASM_PFX(ArmEnableIrq):\r
- msr daifclr, #DAIF_IRQ_BIT\r
+ msr daifclr, #DAIF_WR_IRQ_BIT\r
isb\r
ret\r
\r
\r
ASM_PFX(ArmDisableIrq):\r
- msr daifset, #DAIF_IRQ_BIT\r
+ msr daifset, #DAIF_WR_IRQ_BIT\r
isb\r
ret\r
\r
\r
ASM_PFX(ArmEnableFiq):\r
- msr daifclr, #DAIF_FIQ_BIT\r
+ msr daifclr, #DAIF_WR_FIQ_BIT\r
isb\r
ret\r
\r
\r
ASM_PFX(ArmDisableFiq):\r
- msr daifset, #DAIF_FIQ_BIT\r
+ msr daifset, #DAIF_WR_FIQ_BIT\r
isb\r
ret\r
\r
\r
ASM_PFX(ArmEnableInterrupts):\r
- msr daifclr, #DAIF_INT_BITS\r
+ msr daifclr, #DAIF_WR_INT_BITS\r
isb\r
ret\r
\r
\r
ASM_PFX(ArmDisableInterrupts):\r
- msr daifset, #DAIF_INT_BITS\r
+ msr daifset, #DAIF_WR_INT_BITS\r
isb\r
ret\r
\r
\r
ASM_PFX(ArmDisableAllExceptions):\r
- msr daifset, #DAIF_ALL\r
+ msr daifset, #DAIF_WR_ALL\r
isb\r
ret\r
\r