ArmPkg/ArmLib: remove unused ARM9 support

[mirror_edk2.git] / ArmPkg / Library / ArmLib / Arm9 / Arm9Support.S

diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
deleted file mode 100644 (file)
index c708d21..0000000
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
+++ /dev/null
@@ -1,153 +0,0 @@
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution.  The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-.text\r
-.align 2\r
-GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)\r
-GCC_ASM_EXPORT(ArmCleanDataCache)\r
-GCC_ASM_EXPORT(ArmInvalidateDataCache)\r
-GCC_ASM_EXPORT(ArmInvalidateInstructionCache)\r
-GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)\r
-GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)\r
-GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)\r
-GCC_ASM_EXPORT(ArmEnableMmu)\r
-GCC_ASM_EXPORT(ArmDisableMmu)\r
-GCC_ASM_EXPORT(ArmMmuEnabled)\r
-GCC_ASM_EXPORT(ArmEnableDataCache)\r
-GCC_ASM_EXPORT(ArmDisableDataCache)\r
-GCC_ASM_EXPORT(ArmEnableInstructionCache)\r
-GCC_ASM_EXPORT(ArmDisableInstructionCache)\r
-GCC_ASM_EXPORT(ArmEnableBranchPrediction)\r
-GCC_ASM_EXPORT(ArmDisableBranchPrediction)\r
-GCC_ASM_EXPORT(ArmDataMemoryBarrier)\r
-GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)\r
-GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)\r
-\r
-\r
-.set DC_ON, (1<<2)\r
-.set IC_ON, (1<<12)\r
-\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r
-  mcr     p15, 0, r0, c7, c6, 1   @ invalidate single data cache line\r
-  bx      lr\r
-\r
-ASM_PFX(ArmCleanDataCacheEntryByMVA):\r
-  mcr     p15, 0, r0, c7, c10, 1  @ clean single data cache line\r
-  bx      lr\r
-\r
-ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):\r
-  mcr     p15, 0, r0, c7, c14, 1  @ clean and invalidate single data cache line\r
-  bx      lr\r
-\r
-ASM_PFX(ArmEnableInstructionCache):\r
-  ldr    r1,=IC_ON\r
-  mrc    p15,0,r0,c1,c0,0     @Read control register configuration data\r
-  orr    r0,r0,r1             @Set I bit\r
-  mcr    p15,0,r0,c1,c0,0     @Write control register configuration data\r
-  bx     LR\r
-\r
-ASM_PFX(ArmDisableInstructionCache):\r
-  ldr    r1,=IC_ON\r
-  mrc    p15,0,r0,c1,c0,0     @Read control register configuration data\r
-  bic    r0,r0,r1             @Clear I bit.\r
-  mcr    p15,0,r0,c1,c0,0     @Write control register configuration data\r
-  bx     LR\r
-\r
-ASM_PFX(ArmInvalidateInstructionCache):\r
-  mov     r0,#0\r
-  mcr     p15,0,r0,c7,c5,0     @Invalidate entire Instruction cache.\r
-                         @Also flushes the branch target cache.\r
-  mov     r0,#0\r
-  mcr     p15,0,r0,c7,c10,4    @Data write buffer\r
-  bx      LR\r
-\r
-ASM_PFX(ArmEnableMmu):\r
-  mrc     p15,0,R0,c1,c0,0\r
-  orr     R0,R0,#1\r
-  mcr     p15,0,R0,c1,c0,0\r
-  bx      LR\r
-\r
-ASM_PFX(ArmMmuEnabled):\r
-  mrc     p15,0,R0,c1,c0,0\r
-  and     R0,R0,#1\r
-  bx      LR\r
-\r
-ASM_PFX(ArmDisableMmu):\r
-  mrc     p15,0,R0,c1,c0,0\r
-  bic     R0,R0,#1\r
-  mcr     p15,0,R0,c1,c0,0\r
-  mov     R0,#0\r
-  mcr     p15,0,R0,c7,c10,4     @Drain write buffer\r
-  bx      LR\r
-\r
-ASM_PFX(ArmEnableDataCache):\r
-  ldr     R1,=DC_ON\r
-  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data\r
-  orr     R0,R0,R1              @Set C bit\r
-  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data\r
-  bx      LR\r
-\r
-ASM_PFX(ArmDisableDataCache):\r
-  ldr     R1,=DC_ON\r
-  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data\r
-  bic     R0,R0,R1              @Clear C bit\r
-  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data\r
-  bx      LR\r
-\r
-ASM_PFX(ArmCleanDataCache):\r
-  mrc     p15,0,r15,c7,c10,3\r
-  bne     ASM_PFX(ArmCleanDataCache)\r
-  mov     R0,#0\r
-  mcr     p15,0,R0,c7,c10,4  @Drain write buffer\r
-  bx      LR\r
-\r
-ASM_PFX(ArmInvalidateDataCache):\r
-  mov     R0,#0\r
-  mcr     p15,0,R0,c7,c6,0        @Invalidate entire data cache\r
-  mov     R0,#0\r
-  mcr     p15,0,R0,c7,c10,4       @Drain write buffer\r
-  bx      LR\r
-\r
-ASM_PFX(ArmCleanInvalidateDataCache):\r
-  mrc     p15,0,r15,c7,c14,3\r
-  bne     ASM_PFX(ArmCleanInvalidateDataCache)\r
-  mov     R0,#0\r
-  mcr     p15,0,R0,c7,c10,4        @Drain write buffer\r
-  bx      LR\r
-\r
-ASM_PFX(ArmEnableBranchPrediction):\r
-  bx      LR                      @Branch prediction is not supported.\r
-\r
-ASM_PFX(ArmDisableBranchPrediction):\r
-  bx      LR                      @Branch prediction is not supported.\r
-\r
-ASM_PFX(ArmDataMemoryBarrier):\r
-  mov R0, #0\r
-  mcr P15, #0, R0, C7, C10, #5    @ check if this is OK?\r
-  bx      LR\r
-\r
-ASM_PFX(ArmDataSyncronizationBarrier):\r
-  mov R0, #0\r
-  mcr P15, #0, R0, C7, C10, #4   @ check if this is OK?\r
-  bx      LR\r
-\r
-ASM_PFX(ArmInstructionSynchronizationBarrier):\r
-  mov R0, #0\r
-  mcr P15, #0, R0, C7, C5, #4     @ check if this is OK?\r
-  bx      LR\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
-\r