+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#ifndef __ARM926EJ_S_H__\r
-#define __ARM926EJ_S_H__\r
-\r
-// Domain Access Control Register\r
-#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))\r
-#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))\r
-#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))\r
-#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))\r
-#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))\r
-\r
-#define TRANSLATION_TABLE_SIZE (16 * 1024)\r
-#define TRANSLATION_TABLE_ALIGNMENT (16 * 1024)\r
-#define TRANSLATION_TABLE_ALIGNMENT_MASK (TRANSLATION_TABLE_ALIGNMENT - 1)\r
-\r
-#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))\r
-\r
-// Translation table descriptor types\r
-#define TT_DESCRIPTOR_TYPE_MASK (3UL << 0)\r
-#define TT_DESCRIPTOR_TYPE_FAULT (0UL << 0)\r
-#define TT_DESCRIPTOR_TYPE_COARSE ((1UL << 0) | (1UL << 4))\r
-#define TT_DESCRIPTOR_TYPE_SECTION ((2UL << 0) | (1UL << 4))\r
-#define TT_DESCRIPTOR_TYPE_FINE ((3UL << 0) | (1UL << 4))\r
-\r
-// Section descriptor definitions\r
-#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)\r
-\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK (3UL << 2)\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_UNCACHED_UNBUFFERED (0UL << 2)\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_UNCACHED_BUFFERED (1UL << 2)\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH (2UL << 2)\r
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK (3UL << 2)\r
-\r
-#define TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_MASK (3UL << 10)\r
-#define TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_NONE (1UL << 10)\r
-#define TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_ONLY (2UL << 10)\r
-#define TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_WRITE (3UL << 10)\r
-\r
-#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)\r
-#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0xF) << 5)\r
-\r
-#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)\r
-#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) (a & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)\r
-\r
-#define TT_DESCRIPTOR_SECTION_WRITE_BACK (TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_WRITE | \\r
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK | \\r
- TT_DESCRIPTOR_TYPE_SECTION)\r
-#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH (TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_WRITE | \\r
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH | \\r
- TT_DESCRIPTOR_TYPE_SECTION)\r
-#define TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED (TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_WRITE | \\r
- TT_DESCRIPTOR_SECTION_DOMAIN(0) | \\r
- TT_DESCRIPTOR_SECTION_CACHE_POLICY_UNCACHED_UNBUFFERED | \\r
- TT_DESCRIPTOR_TYPE_SECTION)\r
-\r
-#endif // __ARM926EJ_S_H__\r
+++ /dev/null
-#/** @file\r
-# Semihosting serail port lib\r
-#\r
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = Arm9ArmLib\r
- FILE_GUID = 375D70D3-91E0-4374-A540-68BD959EB184\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmLib\r
-\r
-[Sources.common]\r
- ../Common/Arm/ArmLibSupport.S | GCC\r
- ../Common/Arm/ArmLibSupport.asm | RVCT\r
- ../Common/ArmLib.c\r
-\r
- Arm9Support.S | GCC\r
- Arm9Support.asm | RVCT\r
-\r
- Arm9Lib.c\r
- Arm9CacheInformation.c\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- MemoryAllocationLib\r
-\r
-[Protocols]\r
- gEfiCpuArchProtocolGuid\r
+++ /dev/null
-#/** @file\r
-# Semihosting serail port lib\r
-#\r
-# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = Arm9ArmLibPrePi\r
- FILE_GUID = e9b6011f-ee15-4e59-ab8f-a819a081fa54\r
- MODULE_TYPE = DXE_DRIVER\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmLib\r
-\r
-[Sources.common]\r
- ../Common/Arm/ArmLibSupport.S | GCC\r
- ../Common/Arm/ArmLibSupport.asm | RVCT\r
- ../Common/ArmLib.c\r
-\r
- Arm9Support.S | GCC\r
- Arm9Support.asm | RVCT\r
-\r
- Arm9Lib.c\r
- Arm9CacheInformation.c\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- MdePkg/MdePkg.dec\r
-\r
-[LibraryClasses]\r
- PrePiLib\r
-\r
-[Protocols]\r
- gEfiCpuArchProtocolGuid\r
+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
- Copyright (c) 2014, ARM Limited. All rights reserved.\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <Library/ArmLib.h>\r
-#include "ArmLibPrivate.h"\r
-\r
-ARM_CACHE_TYPE\r
-EFIAPI\r
-ArmCacheType (\r
- VOID\r
- )\r
-{\r
- switch (CACHE_TYPE (ArmCacheInfo ()))\r
- {\r
- case CACHE_TYPE_WRITE_BACK: return ARM_CACHE_TYPE_WRITE_BACK;\r
- default: return ARM_CACHE_TYPE_UNKNOWN;\r
- }\r
-}\r
-\r
-ARM_CACHE_ARCHITECTURE\r
-EFIAPI\r
-ArmCacheArchitecture (\r
- VOID\r
- )\r
-{\r
- switch (CACHE_ARCHITECTURE (ArmCacheInfo ()))\r
- {\r
- case CACHE_ARCHITECTURE_UNIFIED: return ARM_CACHE_ARCHITECTURE_UNIFIED;\r
- case CACHE_ARCHITECTURE_SEPARATE: return ARM_CACHE_ARCHITECTURE_SEPARATE;\r
- default: return ARM_CACHE_ARCHITECTURE_UNKNOWN;\r
- }\r
-}\r
-\r
-BOOLEAN\r
-EFIAPI\r
-ArmDataCachePresent (\r
- VOID\r
- )\r
-{\r
- switch (DATA_CACHE_PRESENT (ArmCacheInfo ()))\r
- {\r
- case CACHE_PRESENT: return TRUE;\r
- case CACHE_NOT_PRESENT: return FALSE;\r
- default: return FALSE;\r
- }\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-ArmDataCacheSize (\r
- VOID\r
- )\r
-{\r
- switch (DATA_CACHE_SIZE (ArmCacheInfo ()))\r
- {\r
- case CACHE_SIZE_4_KB: return 4 * 1024;\r
- case CACHE_SIZE_8_KB: return 8 * 1024;\r
- case CACHE_SIZE_16_KB: return 16 * 1024;\r
- case CACHE_SIZE_32_KB: return 32 * 1024;\r
- case CACHE_SIZE_64_KB: return 64 * 1024;\r
- case CACHE_SIZE_128_KB: return 128 * 1024;\r
- default: return 0;\r
- }\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-ArmDataCacheAssociativity (\r
- VOID\r
- )\r
-{\r
- switch (DATA_CACHE_ASSOCIATIVITY (ArmCacheInfo ()))\r
- {\r
- case CACHE_ASSOCIATIVITY_4_WAY: return 4;\r
- case CACHE_ASSOCIATIVITY_DIRECT: return 1;\r
- default: return 0;\r
- }\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-ArmDataCacheLineLength (\r
- VOID\r
- )\r
-{\r
- switch (DATA_CACHE_LINE_LENGTH (ArmCacheInfo ()))\r
- {\r
- case CACHE_LINE_LENGTH_32_BYTES: return 32;\r
- default: return 0;\r
- }\r
-}\r
-\r
-BOOLEAN\r
-EFIAPI\r
-ArmInstructionCachePresent (\r
- VOID\r
- )\r
-{\r
- switch (INSTRUCTION_CACHE_PRESENT (ArmCacheInfo ()))\r
- {\r
- case CACHE_PRESENT: return TRUE;\r
- case CACHE_NOT_PRESENT: return FALSE;\r
- default: return FALSE;\r
- }\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-ArmInstructionCacheSize (\r
- VOID\r
- )\r
-{\r
- switch (INSTRUCTION_CACHE_SIZE (ArmCacheInfo ()))\r
- {\r
- case CACHE_SIZE_4_KB: return 4 * 1024;\r
- case CACHE_SIZE_8_KB: return 8 * 1024;\r
- case CACHE_SIZE_16_KB: return 16 * 1024;\r
- case CACHE_SIZE_32_KB: return 32 * 1024;\r
- case CACHE_SIZE_64_KB: return 64 * 1024;\r
- case CACHE_SIZE_128_KB: return 128 * 1024;\r
- default: return 0;\r
- }\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-ArmInstructionCacheAssociativity (\r
- VOID\r
- )\r
-{\r
- switch (INSTRUCTION_CACHE_ASSOCIATIVITY (ArmCacheInfo ()))\r
- {\r
- case CACHE_ASSOCIATIVITY_8_WAY: return 8;\r
- case CACHE_ASSOCIATIVITY_4_WAY: return 4;\r
- case CACHE_ASSOCIATIVITY_DIRECT: return 1;\r
- default: return 0;\r
- }\r
-}\r
-\r
-UINTN\r
-EFIAPI\r
-ArmInstructionCacheLineLength (\r
- VOID\r
- )\r
-{\r
- switch (INSTRUCTION_CACHE_LINE_LENGTH (ArmCacheInfo ()))\r
- {\r
- case CACHE_LINE_LENGTH_32_BYTES: return 32;\r
- default: return 0;\r
- }\r
-}\r
-\r
-\r
+++ /dev/null
-/** @file\r
-\r
- Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
- Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <Chipset/ARM926EJ-S.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <Library/DebugLib.h>\r
-\r
-VOID\r
-FillTranslationTable (\r
- IN UINT32 *TranslationTable,\r
- IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion\r
- )\r
-{\r
- UINT32 *Entry;\r
- UINTN Sections;\r
- UINTN Index;\r
- UINT32 Attributes;\r
- UINT32 PhysicalBase = MemoryRegion->PhysicalBase;\r
-\r
- switch (MemoryRegion->Attributes) {\r
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:\r
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;\r
- break;\r
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:\r
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;\r
- break;\r
- case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:\r
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;\r
- break;\r
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:\r
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:\r
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:\r
- ASSERT(0); // Trustzone is not supported on ARMv5\r
- default:\r
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;\r
- break;\r
- }\r
-\r
- Entry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);\r
- Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;\r
-\r
- // The current code does not support memory region size that is not aligned on TT_DESCRIPTOR_SECTION_SIZE boundary\r
- ASSERT (MemoryRegion->Length % TT_DESCRIPTOR_SECTION_SIZE == 0);\r
-\r
- for (Index = 0; Index < Sections; Index++)\r
- {\r
- *Entry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;\r
- PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;\r
- }\r
-}\r
-\r
-RETURN_STATUS\r
-EFIAPI\r
-ArmConfigureMmu (\r
- IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,\r
- OUT VOID **TranslationTableBase OPTIONAL,\r
- OUT UINTN *TranslationTableSize OPTIONAL\r
- )\r
-{\r
- VOID *TranslationTable;\r
-\r
- // Allocate pages for translation table.\r
- TranslationTable = AllocatePages (EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));\r
- if (TranslationTable == NULL) {\r
- return RETURN_OUT_OF_RESOURCES;\r
- }\r
- TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);\r
-\r
- if (TranslationTableBase != NULL) {\r
- *TranslationTableBase = TranslationTable;\r
- }\r
-\r
- if (TranslationTableBase != NULL) {\r
- *TranslationTableSize = TRANSLATION_TABLE_SIZE;\r
- }\r
-\r
- ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);\r
-\r
- ArmCleanInvalidateDataCache();\r
- ArmInvalidateInstructionCache();\r
- ArmInvalidateTlb();\r
-\r
- ArmDisableDataCache();\r
- ArmDisableInstructionCache();\r
- ArmDisableMmu();\r
-\r
- // Make sure nothing sneaked into the cache\r
- ArmCleanInvalidateDataCache();\r
- ArmInvalidateInstructionCache();\r
-\r
- while (MemoryTable->Length != 0) {\r
- FillTranslationTable(TranslationTable, MemoryTable);\r
- MemoryTable++;\r
- }\r
-\r
- ArmSetTTBR0(TranslationTable);\r
-\r
- ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |\r
- DOMAIN_ACCESS_CONTROL_NONE(14) |\r
- DOMAIN_ACCESS_CONTROL_NONE(13) |\r
- DOMAIN_ACCESS_CONTROL_NONE(12) |\r
- DOMAIN_ACCESS_CONTROL_NONE(11) |\r
- DOMAIN_ACCESS_CONTROL_NONE(10) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 9) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 8) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 7) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 6) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 5) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 4) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 3) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 2) |\r
- DOMAIN_ACCESS_CONTROL_NONE( 1) |\r
- DOMAIN_ACCESS_CONTROL_MANAGER(0));\r
-\r
- ArmEnableInstructionCache();\r
- ArmEnableDataCache();\r
- ArmEnableMmu();\r
-\r
- return RETURN_SUCCESS;\r
-}\r
+++ /dev/null
-#------------------------------------------------------------------------------\r
-#\r
-# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#------------------------------------------------------------------------------\r
-\r
-.text\r
-.align 2\r
-GCC_ASM_EXPORT(ArmCleanInvalidateDataCache)\r
-GCC_ASM_EXPORT(ArmCleanDataCache)\r
-GCC_ASM_EXPORT(ArmInvalidateDataCache)\r
-GCC_ASM_EXPORT(ArmInvalidateInstructionCache)\r
-GCC_ASM_EXPORT(ArmInvalidateDataCacheEntryByMVA)\r
-GCC_ASM_EXPORT(ArmCleanDataCacheEntryByMVA)\r
-GCC_ASM_EXPORT(ArmCleanInvalidateDataCacheEntryByMVA)\r
-GCC_ASM_EXPORT(ArmEnableMmu)\r
-GCC_ASM_EXPORT(ArmDisableMmu)\r
-GCC_ASM_EXPORT(ArmMmuEnabled)\r
-GCC_ASM_EXPORT(ArmEnableDataCache)\r
-GCC_ASM_EXPORT(ArmDisableDataCache)\r
-GCC_ASM_EXPORT(ArmEnableInstructionCache)\r
-GCC_ASM_EXPORT(ArmDisableInstructionCache)\r
-GCC_ASM_EXPORT(ArmEnableBranchPrediction)\r
-GCC_ASM_EXPORT(ArmDisableBranchPrediction)\r
-GCC_ASM_EXPORT(ArmDataMemoryBarrier)\r
-GCC_ASM_EXPORT(ArmDataSyncronizationBarrier)\r
-GCC_ASM_EXPORT(ArmInstructionSynchronizationBarrier)\r
-\r
-\r
-.set DC_ON, (1<<2)\r
-.set IC_ON, (1<<12)\r
-\r
-#------------------------------------------------------------------------------\r
-\r
-ASM_PFX(ArmInvalidateDataCacheEntryByMVA):\r
- mcr p15, 0, r0, c7, c6, 1 @ invalidate single data cache line\r
- bx lr\r
-\r
-ASM_PFX(ArmCleanDataCacheEntryByMVA):\r
- mcr p15, 0, r0, c7, c10, 1 @ clean single data cache line\r
- bx lr\r
-\r
-ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):\r
- mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate single data cache line\r
- bx lr\r
-\r
-ASM_PFX(ArmEnableInstructionCache):\r
- ldr r1,=IC_ON\r
- mrc p15,0,r0,c1,c0,0 @Read control register configuration data\r
- orr r0,r0,r1 @Set I bit\r
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
- bx LR\r
-\r
-ASM_PFX(ArmDisableInstructionCache):\r
- ldr r1,=IC_ON\r
- mrc p15,0,r0,c1,c0,0 @Read control register configuration data\r
- bic r0,r0,r1 @Clear I bit.\r
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
- bx LR\r
-\r
-ASM_PFX(ArmInvalidateInstructionCache):\r
- mov r0,#0\r
- mcr p15,0,r0,c7,c5,0 @Invalidate entire Instruction cache.\r
- @Also flushes the branch target cache.\r
- mov r0,#0\r
- mcr p15,0,r0,c7,c10,4 @Data write buffer\r
- bx LR\r
-\r
-ASM_PFX(ArmEnableMmu):\r
- mrc p15,0,R0,c1,c0,0\r
- orr R0,R0,#1\r
- mcr p15,0,R0,c1,c0,0\r
- bx LR\r
-\r
-ASM_PFX(ArmMmuEnabled):\r
- mrc p15,0,R0,c1,c0,0\r
- and R0,R0,#1\r
- bx LR\r
-\r
-ASM_PFX(ArmDisableMmu):\r
- mrc p15,0,R0,c1,c0,0\r
- bic R0,R0,#1\r
- mcr p15,0,R0,c1,c0,0\r
- mov R0,#0\r
- mcr p15,0,R0,c7,c10,4 @Drain write buffer\r
- bx LR\r
-\r
-ASM_PFX(ArmEnableDataCache):\r
- ldr R1,=DC_ON\r
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
- orr R0,R0,R1 @Set C bit\r
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
- bx LR\r
-\r
-ASM_PFX(ArmDisableDataCache):\r
- ldr R1,=DC_ON\r
- mrc p15,0,R0,c1,c0,0 @Read control register configuration data\r
- bic R0,R0,R1 @Clear C bit\r
- mcr p15,0,r0,c1,c0,0 @Write control register configuration data\r
- bx LR\r
-\r
-ASM_PFX(ArmCleanDataCache):\r
- mrc p15,0,r15,c7,c10,3\r
- bne ASM_PFX(ArmCleanDataCache)\r
- mov R0,#0\r
- mcr p15,0,R0,c7,c10,4 @Drain write buffer\r
- bx LR\r
-\r
-ASM_PFX(ArmInvalidateDataCache):\r
- mov R0,#0\r
- mcr p15,0,R0,c7,c6,0 @Invalidate entire data cache\r
- mov R0,#0\r
- mcr p15,0,R0,c7,c10,4 @Drain write buffer\r
- bx LR\r
-\r
-ASM_PFX(ArmCleanInvalidateDataCache):\r
- mrc p15,0,r15,c7,c14,3\r
- bne ASM_PFX(ArmCleanInvalidateDataCache)\r
- mov R0,#0\r
- mcr p15,0,R0,c7,c10,4 @Drain write buffer\r
- bx LR\r
-\r
-ASM_PFX(ArmEnableBranchPrediction):\r
- bx LR @Branch prediction is not supported.\r
-\r
-ASM_PFX(ArmDisableBranchPrediction):\r
- bx LR @Branch prediction is not supported.\r
-\r
-ASM_PFX(ArmDataMemoryBarrier):\r
- mov R0, #0\r
- mcr P15, #0, R0, C7, C10, #5 @ check if this is OK?\r
- bx LR\r
-\r
-ASM_PFX(ArmDataSyncronizationBarrier):\r
- mov R0, #0\r
- mcr P15, #0, R0, C7, C10, #4 @ check if this is OK?\r
- bx LR\r
-\r
-ASM_PFX(ArmInstructionSynchronizationBarrier):\r
- mov R0, #0\r
- mcr P15, #0, R0, C7, C5, #4 @ check if this is OK?\r
- bx LR\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
-\r
+++ /dev/null
-//------------------------------------------------------------------------------\r
-//\r
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
- EXPORT ArmCleanInvalidateDataCache\r
- EXPORT ArmCleanDataCache\r
- EXPORT ArmInvalidateDataCache\r
- EXPORT ArmInvalidateInstructionCache\r
- EXPORT ArmInvalidateDataCacheEntryByMVA\r
- EXPORT ArmCleanDataCacheEntryByMVA\r
- EXPORT ArmCleanInvalidateDataCacheEntryByMVA\r
- EXPORT ArmEnableMmu\r
- EXPORT ArmDisableMmu\r
- EXPORT ArmMmuEnabled\r
- EXPORT ArmEnableDataCache\r
- EXPORT ArmDisableDataCache\r
- EXPORT ArmEnableInstructionCache\r
- EXPORT ArmDisableInstructionCache\r
- EXPORT ArmEnableBranchPrediction\r
- EXPORT ArmDisableBranchPrediction\r
- EXPORT ArmDataMemoryBarrier\r
- EXPORT ArmDataSyncronizationBarrier\r
- EXPORT ArmInstructionSynchronizationBarrier\r
-\r
-\r
-DC_ON EQU ( 0x1:SHL:2 )\r
-IC_ON EQU ( 0x1:SHL:12 )\r
-\r
- AREA ArmCacheLib, CODE, READONLY\r
- PRESERVE8\r
-\r
-\r
-ArmInvalidateDataCacheEntryByMVA\r
- MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line\r
- BX lr\r
-\r
-\r
-ArmCleanDataCacheEntryByMVA\r
- MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line\r
- BX lr\r
-\r
-\r
-ArmCleanInvalidateDataCacheEntryByMVA\r
- MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line\r
- BX lr\r
-\r
-ArmEnableInstructionCache\r
- LDR R1,=IC_ON\r
- MRC p15,0,R0,c1,c0,0 ;Read control register configuration data\r
- ORR R0,R0,R1 ;Set I bit\r
- MCR p15,0,r0,c1,c0,0 ;Write control register configuration data\r
- BX LR\r
-\r
-ArmDisableInstructionCache\r
- LDR R1,=IC_ON\r
- MRC p15,0,R0,c1,c0,0 ;Read control register configuration data\r
- BIC R0,R0,R1 ;Clear I bit.\r
- MCR p15,0,r0,c1,c0,0 ;Write control register configuration data\r
- BX LR\r
-\r
-ArmInvalidateInstructionCache\r
- MOV R0,#0\r
- MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache\r
- MOV R0,#0\r
- MCR p15,0,R0,c7,c10,4 ;Drain write buffer\r
- BX LR\r
-\r
-ArmEnableMmu\r
- mrc p15,0,R0,c1,c0,0\r
- orr R0,R0,#1\r
- mcr p15,0,R0,c1,c0,0\r
- bx LR\r
-\r
-ArmMmuEnabled\r
- mrc p15,0,R0,c1,c0,0\r
- and R0,R0,#1\r
- bx LR\r
-\r
-ArmDisableMmu\r
- mrc p15,0,R0,c1,c0,0\r
- bic R0,R0,#1\r
- mcr p15,0,R0,c1,c0,0\r
- mov R0,#0\r
- mcr p15,0,R0,c7,c10,4 ;Drain write buffer\r
- bx LR\r
-\r
-ArmEnableDataCache\r
- LDR R1,=DC_ON\r
- MRC p15,0,R0,c1,c0,0 ;Read control register configuration data\r
- ORR R0,R0,R1 ;Set C bit\r
- MCR p15,0,r0,c1,c0,0 ;Write control register configuration data\r
- BX LR\r
-\r
-ArmDisableDataCache\r
- LDR R1,=DC_ON\r
- MRC p15,0,R0,c1,c0,0 ;Read control register configuration data\r
- BIC R0,R0,R1 ;Clear C bit\r
- MCR p15,0,r0,c1,c0,0 ;Write control register configuration data\r
- BX LR\r
-\r
-ArmCleanDataCache\r
- MRC p15,0,r15,c7,c10,3\r
- BNE ArmCleanDataCache\r
- MOV R0,#0\r
- MCR p15,0,R0,c7,c10,4 ;Drain write buffer\r
- BX LR\r
-\r
-ArmInvalidateDataCache\r
- MOV R0,#0\r
- MCR p15,0,R0,c7,c6,0 ;Invalidate entire data cache\r
- MOV R0,#0\r
- MCR p15,0,R0,c7,c10,4 ;Drain write buffer\r
- BX LR\r
-\r
-ArmCleanInvalidateDataCache\r
- MRC p15,0,r15,c7,c14,3\r
- BNE ArmCleanInvalidateDataCache\r
- MOV R0,#0\r
- MCR p15,0,R0,c7,c10,4 ;Drain write buffer\r
- BX LR\r
-\r
-ArmEnableBranchPrediction\r
- bx LR ;Branch prediction is not supported.\r
-\r
-ArmDisableBranchPrediction\r
- bx LR ;Branch prediction is not supported.\r
-\r
-ASM_PFX(ArmDataMemoryBarrier):\r
- mov R0, #0\r
- mcr P15, #0, R0, C7, C10, #5 ; Check to see if this is correct\r
- bx LR\r
-\r
-ASM_PFX(ArmDataSyncronizationBarrier):\r
- mov R0, #0\r
- mcr P15, #0, R0, C7, C10, #4 ; Check to see if this is correct\r
- bx LR\r
-\r
-ASM_PFX(ArmInstructionSynchronizationBarrier):\r
- MOV R0, #0\r
- MCR P15, #0, R0, C7, C5, #4 ; Check to see if this is correct\r
- bx LR\r
-\r
- END\r
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