ArmPkg/ArmLib: remove unused ARM9 support

[mirror_edk2.git] / ArmPkg / Library / ArmLib / Arm9 / Arm9Support.asm

diff --git a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm b/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
deleted file mode 100644 (file)
index 4aaa546..0000000
--- a/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
+++ /dev/null
@@ -1,153 +0,0 @@
-//------------------------------------------------------------------------------\r
-//\r
-// Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution.  The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//------------------------------------------------------------------------------\r
-\r
-    EXPORT  ArmCleanInvalidateDataCache\r
-    EXPORT  ArmCleanDataCache\r
-    EXPORT  ArmInvalidateDataCache\r
-    EXPORT  ArmInvalidateInstructionCache\r
-    EXPORT  ArmInvalidateDataCacheEntryByMVA\r
-    EXPORT  ArmCleanDataCacheEntryByMVA\r
-    EXPORT  ArmCleanInvalidateDataCacheEntryByMVA\r
-    EXPORT  ArmEnableMmu\r
-    EXPORT  ArmDisableMmu\r
-    EXPORT  ArmMmuEnabled\r
-    EXPORT  ArmEnableDataCache\r
-    EXPORT  ArmDisableDataCache\r
-    EXPORT  ArmEnableInstructionCache\r
-    EXPORT  ArmDisableInstructionCache\r
-    EXPORT  ArmEnableBranchPrediction\r
-    EXPORT  ArmDisableBranchPrediction\r
-    EXPORT  ArmDataMemoryBarrier\r
-    EXPORT  ArmDataSyncronizationBarrier\r
-    EXPORT  ArmInstructionSynchronizationBarrier\r
-\r
-\r
-DC_ON       EQU     ( 0x1:SHL:2 )\r
-IC_ON       EQU     ( 0x1:SHL:12 )\r
-\r
-    AREA    ArmCacheLib, CODE, READONLY\r
-    PRESERVE8\r
-\r
-\r
-ArmInvalidateDataCacheEntryByMVA\r
-  MCR     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line\r
-  BX      lr\r
-\r
-\r
-ArmCleanDataCacheEntryByMVA\r
-  MCR     p15, 0, r0, c7, c10, 1  ; clean single data cache line\r
-  BX      lr\r
-\r
-\r
-ArmCleanInvalidateDataCacheEntryByMVA\r
-  MCR     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line\r
-  BX      lr\r
-\r
-ArmEnableInstructionCache\r
-  LDR     R1,=IC_ON\r
-  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data\r
-  ORR     R0,R0,R1             ;Set I bit\r
-  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data\r
-  BX      LR\r
-\r
-ArmDisableInstructionCache\r
-  LDR     R1,=IC_ON\r
-  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data\r
-  BIC     R0,R0,R1             ;Clear I bit.\r
-  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data\r
-  BX      LR\r
-\r
-ArmInvalidateInstructionCache\r
-  MOV     R0,#0\r
-  MCR     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache\r
-  MOV     R0,#0\r
-  MCR     p15,0,R0,c7,c10,4     ;Drain write buffer\r
-  BX      LR\r
-\r
-ArmEnableMmu\r
-  mrc     p15,0,R0,c1,c0,0\r
-  orr     R0,R0,#1\r
-  mcr     p15,0,R0,c1,c0,0\r
-  bx      LR\r
-\r
-ArmMmuEnabled\r
-  mrc     p15,0,R0,c1,c0,0\r
-  and     R0,R0,#1\r
-  bx      LR\r
-\r
-ArmDisableMmu\r
-  mrc     p15,0,R0,c1,c0,0\r
-  bic     R0,R0,#1\r
-  mcr     p15,0,R0,c1,c0,0\r
-  mov     R0,#0\r
-  mcr     p15,0,R0,c7,c10,4     ;Drain write buffer\r
-  bx      LR\r
-\r
-ArmEnableDataCache\r
-  LDR     R1,=DC_ON\r
-  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data\r
-  ORR     R0,R0,R1              ;Set C bit\r
-  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data\r
-  BX      LR\r
-\r
-ArmDisableDataCache\r
-  LDR     R1,=DC_ON\r
-  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data\r
-  BIC     R0,R0,R1              ;Clear C bit\r
-  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data\r
-  BX      LR\r
-\r
-ArmCleanDataCache\r
-  MRC     p15,0,r15,c7,c10,3\r
-  BNE     ArmCleanDataCache\r
-  MOV     R0,#0\r
-  MCR     p15,0,R0,c7,c10,4      ;Drain write buffer\r
-  BX      LR\r
-\r
-ArmInvalidateDataCache\r
-  MOV     R0,#0\r
-  MCR     p15,0,R0,c7,c6,0      ;Invalidate entire data cache\r
-  MOV     R0,#0\r
-  MCR     p15,0,R0,c7,c10,4     ;Drain write buffer\r
-  BX      LR\r
-\r
-ArmCleanInvalidateDataCache\r
-  MRC     p15,0,r15,c7,c14,3\r
-  BNE     ArmCleanInvalidateDataCache\r
-  MOV     R0,#0\r
-  MCR     p15,0,R0,c7,c10,4      ;Drain write buffer\r
-  BX      LR\r
-\r
-ArmEnableBranchPrediction\r
-  bx      LR                    ;Branch prediction is not supported.\r
-\r
-ArmDisableBranchPrediction\r
-  bx      LR                    ;Branch prediction is not supported.\r
-\r
-ASM_PFX(ArmDataMemoryBarrier):\r
-  mov R0, #0\r
-  mcr P15, #0, R0, C7, C10, #5  ; Check to see if this is correct\r
-  bx      LR\r
-\r
-ASM_PFX(ArmDataSyncronizationBarrier):\r
-  mov R0, #0\r
-  mcr P15, #0, R0, C7, C10, #4 ; Check to see if this is correct\r
-  bx      LR\r
-\r
-ASM_PFX(ArmInstructionSynchronizationBarrier):\r
-  MOV R0, #0\r
-  MCR P15, #0, R0, C7, C5, #4 ; Check to see if this is correct\r
-  bx      LR\r
-\r
-    END\r