ARM Packages: Removed trailing spaces

[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Mmu.c

diff --git a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
index 0f8b814c63b288dfb5c69256e01907e3fb4bcd3c..d035ff3caa404b64017f412482f8305d8068e288 100644 (file)
--- a/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
+++ b/ArmPkg/Library/ArmLib/ArmV7/ArmV7Mmu.c
@@ -2,18 +2,18 @@
 *  File managing the MMU for ARMv7 architecture\r
 *\r
 *  Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-*  \r
-*  This program and the accompanying materials                          \r
-*  are licensed and made available under the terms and conditions of the BSD License         \r
-*  which accompanies this distribution.  The full text of the license may be found at        \r
-*  http://opensource.org/licenses/bsd-license.php                                            \r
 *\r
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+*  This program and the accompanying materials\r
+*  are licensed and made available under the terms and conditions of the BSD License\r
+*  which accompanies this distribution.  The full text of the license may be found at\r
+*  http://opensource.org/licenses/bsd-license.php\r
+*\r
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
 *\r
 **/\r
 \r
-#include <Uefi.h> \r
+#include <Uefi.h>\r
 #include <Chipset/ArmV7.h>\r
 #include <Library/BaseMemoryLib.h>\r
 #include <Library/MemoryAllocationLib.h>\r
@@ -23,6 +23,24 @@
 #include "ArmV7Lib.h"\r
 #include "ArmLibPrivate.h"\r
 \r
+UINT32\r
+ConvertSectionAttributesToPageAttributes (\r
+  IN UINT32   SectionAttributes,\r
+  IN BOOLEAN  IsLargePage\r
+  )\r
+{\r
+  UINT32 PageAttributes;\r
+\r
+  PageAttributes = 0;\r
+  PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionAttributes, IsLargePage);\r
+  PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes);\r
+  PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes, IsLargePage);\r
+  PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG (SectionAttributes);\r
+  PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S (SectionAttributes);\r
+\r
+  return PageAttributes;\r
+}\r
+\r
 STATIC\r
 VOID\r
 PopulateLevel2PageTable (\r
@@ -76,12 +94,7 @@ PopulateLevel2PageTable (
       TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK;\r
 \r
       // Translate the Section Descriptor into Page Descriptor\r
-      SectionDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE;\r
-      SectionDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(*SectionEntry,0);\r
-      SectionDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(*SectionEntry);\r
-      SectionDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(*SectionEntry,0);\r
-      SectionDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(*SectionEntry);\r
-      SectionDescriptor |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S(*SectionEntry);\r
+      SectionDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (*SectionEntry, FALSE);\r
 \r
       BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(*SectionEntry);\r
 \r
@@ -132,7 +145,7 @@ FillTranslationTable (
   UINT32  Attributes;\r
   UINT32  PhysicalBase = MemoryRegion->PhysicalBase;\r
   UINT32  RemainLength = MemoryRegion->Length;\r
-  \r
+\r
   ASSERT(MemoryRegion->Length > 0);\r
 \r
   switch (MemoryRegion->Attributes) {\r
@@ -164,7 +177,7 @@ FillTranslationTable (
       Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);\r
       break;\r
   }\r
-  \r
+\r
   // Get the first section entry for this mapping\r
   SectionEntry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);\r
 \r
@@ -218,25 +231,13 @@ ArmConfigureMmu (
   if (TranslationTableBase != NULL) {\r
     *TranslationTableBase = TranslationTable;\r
   }\r
-  \r
+\r
   if (TranslationTableSize != NULL) {\r
     *TranslationTableSize = TRANSLATION_TABLE_SECTION_SIZE;\r
   }\r
 \r
   ZeroMem (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE);\r
 \r
-  ArmCleanInvalidateDataCache ();\r
-  ArmInvalidateInstructionCache ();\r
-\r
-  ArmDisableDataCache ();\r
-  ArmDisableInstructionCache();\r
-  // TLBs are also invalidated when calling ArmDisableMmu()\r
-  ArmDisableMmu ();\r
-\r
-  // Make sure nothing sneaked into the cache\r
-  ArmCleanInvalidateDataCache ();\r
-  ArmInvalidateInstructionCache ();\r
-\r
   // By default, mark the translation table as belonging to a uncached region\r
   TranslationTableAttribute = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;\r
   while (MemoryTable->Length != 0) {\r
@@ -250,13 +251,13 @@ ArmConfigureMmu (
   }\r
 \r
   // Translate the Memory Attributes into Translation Table Register Attributes\r
-  if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) || \r
+  if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) ||\r
       (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {\r
     TTBRAttributes = TTBR_NON_CACHEABLE;\r
-  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) || \r
+  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||\r
       (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {\r
     TTBRAttributes = TTBR_WRITE_BACK_ALLOC;\r
-  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) || \r
+  } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||\r
       (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {\r
     TTBRAttributes = TTBR_WRITE_THROUGH_NO_ALLOC;\r
   } else {\r
@@ -264,8 +265,20 @@ ArmConfigureMmu (
     return RETURN_UNSUPPORTED;\r
   }\r
 \r
+  ArmCleanInvalidateDataCache ();\r
+  ArmInvalidateInstructionCache ();\r
+\r
+  ArmDisableDataCache ();\r
+  ArmDisableInstructionCache();\r
+  // TLBs are also invalidated when calling ArmDisableMmu()\r
+  ArmDisableMmu ();\r
+\r
+  // Make sure nothing sneaked into the cache\r
+  ArmCleanInvalidateDataCache ();\r
+  ArmInvalidateInstructionCache ();\r
+\r
   ArmSetTTBR0 ((VOID *)(UINTN)(((UINTN)TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F)));\r
-    \r
+\r
   ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |\r
                              DOMAIN_ACCESS_CONTROL_NONE(14) |\r
                              DOMAIN_ACCESS_CONTROL_NONE(13) |\r
@@ -282,7 +295,7 @@ ArmConfigureMmu (
                              DOMAIN_ACCESS_CONTROL_NONE( 2) |\r
                              DOMAIN_ACCESS_CONTROL_NONE( 1) |\r
                              DOMAIN_ACCESS_CONTROL_MANAGER(0));\r
-    \r
+\r
   ArmEnableInstructionCache();\r
   ArmEnableDataCache();\r
   ArmEnableMmu();\r