--- /dev/null
+/** @file\r
+* Header defining Versatile Express constants (Base addresses, sizes, flags)\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#ifndef __ARM_VEXPRESS_H__\r
+#define __ARM_VEXPRESS_H__\r
+\r
+/*******************************************\r
+// Platform Memory Map\r
+*******************************************/\r
+\r
+// Can be NOR0, NOR1, DRAM\r
+#define ARM_VE_REMAP_BASE 0x00000000\r
+#define ARM_VE_REMAP_SZ 0x04000000\r
+\r
+// Motherboard Peripheral and On-chip peripheral\r
+#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000\r
+#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ 0x10000000 /* 256 MB */\r
+#define ARM_VE_BOARD_PERIPH_BASE 0x10000000\r
+#define ARM_VE_CHIP_PERIPH_BASE 0x10020000\r
+\r
+// SMC\r
+#define ARM_VE_SMC_BASE 0x40000000\r
+#define ARM_VE_SMC_SZ 0x1C000000\r
+\r
+// NOR Flash 1\r
+#define ARM_VE_SMB_NOR0_BASE 0x40000000\r
+#define ARM_VE_SMB_NOR0_SZ 0x04000000 /* 64 MB */\r
+// NOR Flash 2\r
+#define ARM_VE_SMB_NOR1_BASE 0x44000000\r
+#define ARM_VE_SMB_NOR1_SZ 0x04000000 /* 64 MB */\r
+// SRAM\r
+#define ARM_VE_SMB_SRAM_BASE 0x48000000\r
+#define ARM_VE_SMB_SRAM_SZ 0x02000000 /* 32 MB */\r
+// USB, Ethernet, VRAM\r
+#define ARM_VE_SMB_PERIPH_BASE 0x4C000000\r
+#define ARM_VE_SMB_PERIPH_VRAM 0x4C000000\r
+#define ARM_VE_SMB_PERIPH_SZ 0x04000000 /* 32 MB */\r
+\r
+// DRAM\r
+#define ARM_VE_DRAM_BASE 0x60000000\r
+#define ARM_VE_DRAM_SZ 0x40000000\r
+\r
+// External AXI between daughterboards (Logic Tile)\r
+#define ARM_VE_EXT_AXI_BASE 0xE0000000\r
+#define ARM_VE_EXT_AXI_SZ 0x20000000\r
+\r
+/*******************************************\r
+// Motherboard peripherals\r
+*******************************************/\r
+\r
+// Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)\r
+#define ARM_VE_SYS_FLAGS_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r
+#define ARM_VE_SYS_FLAGS_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)\r
+#define ARM_VE_SYS_FLAGS_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00034)\r
+#define ARM_VE_SYS_FLAGS_NV_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)\r
+#define ARM_VE_SYS_FLAGS_NV_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)\r
+#define ARM_VE_SYS_FLAGS_NV_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)\r
+#define ARM_VE_SYS_PROCID0_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00084)\r
+#define ARM_VE_SYS_PROCID1_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00088)\r
+#define ARM_VE_SYS_CFGDATA_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)\r
+#define ARM_VE_SYS_CFGCTRL_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)\r
+#define ARM_VE_SYS_CFGSTAT_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)\r
+\r
+// SP810 Controller\r
+#define SP810_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x01000)\r
+\r
+// Uart0\r
+#define PL011_CONSOLE_UART_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x09000)\r
+#define PL011_CONSOLE_UART_SPEED 38400\r
+\r
+// SP804 Timer Bases\r
+#define SP804_TIMER0_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x11000)\r
+#define SP804_TIMER1_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x11020)\r
+#define SP804_TIMER2_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x12000)\r
+#define SP804_TIMER3_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x12020)\r
+\r
+// Dynamic Memory Controller Base\r
+#define ARM_VE_DMC_BASE 0x100E0000\r
+\r
+// Static Memory Controller Base\r
+#define ARM_VE_SMC_CTRL_BASE 0x100E1000\r
+\r
+// System Configuration Controller register Base addresses\r
+//#define ARM_VE_SYS_CFG_CTRL_BASE 0x100E2000\r
+#define ARM_VE_SYS_CFGRW0_REG 0x100E2000\r
+#define ARM_VE_SYS_CFGRW1_REG 0x100E2004\r
+#define ARM_VE_SYS_CFGRW2_REG 0x100E2008\r
+\r
+#define ARM_VE_CFGRW1_TZASC_EN_BIT_MASK 0x2000\r
+#define ARM_VE_CFGRW1_REMAP_NOR0 0\r
+#define ARM_VE_CFGRW1_REMAP_NOR1 (1 << 28)\r
+#define ARM_VE_CFGRW1_REMAP_EXT_AXI (1 << 29)\r
+#define ARM_VE_CFGRW1_REMAP_DRAM (1 << 30)\r
+\r
+// TZPC Base Address\r
+#define ARM_VE_TZPC_BASE 0x100E6000\r
+\r
+// PL301 Fast AXI Base Address\r
+#define ARM_VE_FAXI_BASE 0x100E9000\r
+\r
+// TZASC Defintions\r
+#define ARM_VE_TZASC_BASE 0x100EC000\r
+#define ARM_VE_DECPROT_BIT_TZPC (1 << 6)\r
+#define ARM_VE_DECPROT_BIT_DMC_TZASC (1 << 11)\r
+#define ARM_VE_DECPROT_BIT_NMC_TZASC (1 << 12)\r
+#define ARM_VE_DECPROT_BIT_SMC_TZASC (1 << 13)\r
+#define ARM_VE_DECPROT_BIT_EXT_MAST_TZ (1)\r
+#define ARM_VE_DECPROT_BIT_DMC_TZASC_LOCK (1 << 3)\r
+#define ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK (1 << 4)\r
+#define ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK (1 << 5)\r
+\r
+// L2x0 Cache Controller Base Address\r
+//#define ARM_VE_L2x0_CTLR_BASE 0x1E00A000\r
+\r
+\r
+/*******************************************\r
+// Interrupt Map\r
+*******************************************/\r
+\r
+// Timer Interrupts\r
+#define TIMER01_INTERRUPT_NUM 34\r
+#define TIMER23_INTERRUPT_NUM 35\r
+\r
+\r
+/*******************************************\r
+// EFI Memory Map in Permanent Memory (DRAM)\r
+*******************************************/\r
+\r
+// This region is allocated at the bottom of the DRAM. It will be used\r
+// for fixed address allocations such as Vector Table\r
+#define ARM_VE_EFI_FIX_ADDRESS_REGION_SZ SIZE_8MB\r
+\r
+// This region is the memory declared to PEI as permanent memory for PEI\r
+// and DXE. EFI stacks and heaps will be declared in this region.\r
+#define ARM_VE_EFI_MEMORY_REGION_SZ 0x1000000\r
+\r
+\r
+#endif \r
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