ArmPlatformPkg/FVP: map motherboard VRAM as uncached memory

[mirror_edk2.git] / ArmPlatformPkg / ArmVExpressPkg / Library / ArmVExpressLibRTSM / RTSMMem.c

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
index 14c7e8e1d6729f4ca91ef42520b1e5765d22b318..6379e81751fca5e7972c5c30f305be65fd1ae71d 100644 (file)
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
@@ -21,7 +21,7 @@
 #include <ArmPlatform.h>\r
 \r
 // Number of Virtual Memory Map Descriptors\r
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          8\r
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          9\r
 \r
 // DDR attributes\r
 #define DDR_ATTRIBUTES_CACHED   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
@@ -130,6 +130,18 @@ ArmPlatformGetVirtualMemoryMap (
   VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ;\r
   VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
 \r
+  // VRAM\r
+  VirtualMemoryTable[++Index].PhysicalBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE;\r
+  VirtualMemoryTable[Index].VirtualBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE;\r
+  VirtualMemoryTable[Index].Length = PL111_CLCD_VRAM_MOTHERBOARD_SIZE;\r
+  //\r
+  // Map the VRAM region as Normal Non-Cacheable memory and not device memory,\r
+  // so that we can use the accelerated string routines that may use unaligned\r
+  // accesses or DC ZVA instructions. The enum identifier is slightly awkward\r
+  // here, but it maps to a memory type that allows buffering and reordering.\r
+  //\r
+  VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;\r
+\r
   // Map sparse memory region if present\r
   if (HasSparseMemory) {\r
     VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase;\r