ArmPlatformPkg/FVP: map motherboard VRAM as uncached memory

The VRAM of the PL111 on the FVP Base/Foundation models is described as
device memory rather than uncached memory, which is not an accurate
description of the nature of the region (i.e., a framebuffer), and may
result in problems when using accelerated string routines to access the
region, since this may legally involve unaligned accesses or DC ZVA
instructions, which are not allowed on device mappings.

So split of the 8 MB VRAM region into a separate region, and map it using
memory attributes.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h
index 06414e6e7208aa8718c8058fb606bf0e35db0052..d856b6daa1d761656426bf7f3d1d0d95bd950622 100644 (file)
--- a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h
+++ b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h
@@ -40,9 +40,11 @@
 #define ARM_VE_SMB_SRAM_BASE                    0x2E000000\r
 #define ARM_VE_SMB_SRAM_SZ                      SIZE_64KB\r
 // USB, Ethernet, VRAM\r
-#define ARM_VE_SMB_PERIPH_BASE                  0x18000000\r
-#define PL111_CLCD_VRAM_MOTHERBOARD_BASE        ARM_VE_SMB_PERIPH_BASE\r
-#define ARM_VE_SMB_PERIPH_SZ                    SIZE_64MB\r
+#define ARM_VE_SMB_PERIPH_BASE                  0x18800000\r
+#define ARM_VE_SMB_PERIPH_SZ                    (SIZE_64MB - SIZE_8MB)\r
+\r
+#define PL111_CLCD_VRAM_MOTHERBOARD_BASE        0x18000000\r
+#define PL111_CLCD_VRAM_MOTHERBOARD_SIZE        0x800000\r
 \r
 // DRAM\r
 #define ARM_VE_DRAM_BASE                        PcdGet64 (PcdSystemMemoryBase)\r
@@ -74,7 +76,4 @@
 #define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID  1\r
 #define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID  1\r
 \r
-// VRAM offset for the PL111 Colour LCD Controller on the motherboard\r
-#define VRAM_MOTHERBOARD_BASE                     (ARM_VE_SMB_PERIPH_BASE   + 0x00000)\r
-\r
 #endif\r

diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
index 14c7e8e1d6729f4ca91ef42520b1e5765d22b318..6379e81751fca5e7972c5c30f305be65fd1ae71d 100644 (file)
--- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
+++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
@@ -21,7 +21,7 @@
 #include <ArmPlatform.h>\r
 \r
 // Number of Virtual Memory Map Descriptors\r
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          8\r
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          9\r
 \r
 // DDR attributes\r
 #define DDR_ATTRIBUTES_CACHED   ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK\r
@@ -130,6 +130,18 @@ ArmPlatformGetVirtualMemoryMap (
   VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ;\r
   VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;\r
 \r
+  // VRAM\r
+  VirtualMemoryTable[++Index].PhysicalBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE;\r
+  VirtualMemoryTable[Index].VirtualBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE;\r
+  VirtualMemoryTable[Index].Length = PL111_CLCD_VRAM_MOTHERBOARD_SIZE;\r
+  //\r
+  // Map the VRAM region as Normal Non-Cacheable memory and not device memory,\r
+  // so that we can use the accelerated string routines that may use unaligned\r
+  // accesses or DC ZVA instructions. The enum identifier is slightly awkward\r
+  // here, but it maps to a memory type that allows buffering and reordering.\r
+  //\r
+  VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;\r
+\r
   // Map sparse memory region if present\r
   if (HasSparseMemory) {\r
     VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase;\r