--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#include <Library/IoLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Drivers/PL341Dmc.h>\r
+\r
+// Macros for writing to DDR2 controller.\r
+#define DmcWriteReg(reg,val) MmioWrite32(DmcBase + reg, val)\r
+#define DmcReadReg(reg) MmioRead32(DmcBase + reg)\r
+\r
+// Macros for writing/reading to DDR2 PHY controller\r
+#define DmcPhyWriteReg(reg,val) MmioWrite32(DmcPhyBase + reg, val)\r
+#define DmcPhyReadReg(reg) MmioRead32(DmcPhyBase + reg)\r
+\r
+// Initialise PL341 Dynamic Memory Controller\r
+VOID\r
+PL341DmcInit (\r
+ IN PL341_DMC_CONFIG *DmcConfig\r
+ )\r
+{\r
+ UINTN DmcBase;\r
+ UINTN Index;\r
+ UINT32 Chip;\r
+\r
+ DmcBase = DmcConfig->base;\r
+\r
+ // Set config mode\r
+ DmcWriteReg(DMC_COMMAND_REG, DMC_COMMAND_CONFIGURE);\r
+\r
+ //\r
+ // Setup the QoS AXI ID bits\r
+ //\r
+ if (DmcConfig->HasQos) {\r
+ // CLCD AXIID = 000\r
+ DmcWriteReg(DMC_ID_0_CFG_REG, DMC_ID_CFG_QOS_ENABLE | DMC_ID_CFG_QOS_MIN);\r
+\r
+ // Default disable QoS\r
+ DmcWriteReg(DMC_ID_1_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_2_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_3_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_4_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_5_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_6_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_7_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_8_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_9_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_10_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_11_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_12_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_13_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_14_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_15_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ }\r
+\r
+ //\r
+ // Initialise memory controlller\r
+ //\r
+ DmcWriteReg(DMC_REFRESH_PRD_REG, DmcConfig->refresh_prd);\r
+ DmcWriteReg(DMC_CAS_LATENCY_REG, DmcConfig->cas_latency);\r
+ DmcWriteReg(DMC_WRITE_LATENCY_REG, DmcConfig->write_latency);\r
+ DmcWriteReg(DMC_T_MRD_REG, DmcConfig->t_mrd);\r
+ DmcWriteReg(DMC_T_RAS_REG, DmcConfig->t_ras);\r
+ DmcWriteReg(DMC_T_RC_REG, DmcConfig->t_rc);\r
+ DmcWriteReg(DMC_T_RCD_REG, DmcConfig->t_rcd);\r
+ DmcWriteReg(DMC_T_RFC_REG, DmcConfig->t_rfc);\r
+ DmcWriteReg(DMC_T_RP_REG, DmcConfig->t_rp);\r
+ DmcWriteReg(DMC_T_RRD_REG, DmcConfig->t_rrd);\r
+ DmcWriteReg(DMC_T_WR_REG, DmcConfig->t_wr);\r
+ DmcWriteReg(DMC_T_WTR_REG, DmcConfig->t_wtr);\r
+ DmcWriteReg(DMC_T_XP_REG, DmcConfig->t_xp);\r
+ DmcWriteReg(DMC_T_XSR_REG, DmcConfig->t_xsr);\r
+ DmcWriteReg(DMC_T_ESR_REG, DmcConfig->t_esr);\r
+ DmcWriteReg(DMC_T_FAW_REG, DmcConfig->t_faw);\r
+ DmcWriteReg(DMC_T_WRLAT_DIFF, DmcConfig->t_wdata_en);\r
+ DmcWriteReg(DMC_T_RDATA_EN, DmcConfig->t_data_en);\r
+\r
+ //\r
+ // Initialise PL341 Mem Config Registers\r
+ //\r
+\r
+ // Set PL341 Memory Config\r
+ DmcWriteReg(DMC_MEMORY_CONFIG_REG, DmcConfig->MemoryCfg);\r
+\r
+ // Set PL341 Memory Config 2\r
+ DmcWriteReg(DMC_MEMORY_CFG2_REG, DmcConfig->MemoryCfg2);\r
+\r
+ // Set PL341 Chip Select <n>\r
+ DmcWriteReg(DMC_CHIP_0_CFG_REG, DmcConfig->ChipCfg0);\r
+ DmcWriteReg(DMC_CHIP_1_CFG_REG, DmcConfig->ChipCfg1);\r
+ DmcWriteReg(DMC_CHIP_2_CFG_REG, DmcConfig->ChipCfg2);\r
+ DmcWriteReg(DMC_CHIP_3_CFG_REG, DmcConfig->ChipCfg3);\r
+\r
+ // Delay\r
+ for (Index = 0; Index < 10; Index++) {\r
+ DmcReadReg(DMC_STATUS_REG);\r
+ }\r
+\r
+ // Set PL341 Memory Config 3\r
+ DmcWriteReg(DMC_MEMORY_CFG3_REG, DmcConfig->MemoryCfg3);\r
+\r
+ if (DmcConfig->IsUserCfg) {\r
+ //\r
+ // Set Test Chip PHY Registers via PL341 User Config Reg\r
+ // Note that user_cfgX registers are Write Only\r
+ //\r
+ // DLL Freq set = 250MHz - 266MHz\r
+ //\r
+ DmcWriteReg(DMC_USER_0_CFG_REG, DmcConfig->User0Cfg);\r
+\r
+ // user_config2\r
+ // ------------\r
+ // Set defaults before calibrating the DDR2 buffer impendence\r
+ // - Disable ODT\r
+ // - Default drive strengths\r
+ DmcWriteReg(DMC_USER_2_CFG_REG, 0x40000198);\r
+\r
+ //\r
+ // Auto calibrate the DDR2 buffers impendence\r
+ //\r
+ while (!(DmcReadReg(DMC_USER_STATUS_REG) & 0x100));\r
+\r
+ // Set the output driven strength\r
+ DmcWriteReg(DMC_USER_2_CFG_REG, 0x40800000 | DmcConfig->User2Cfg);\r
+\r
+ //\r
+ // Set PL341 Feature Control Register\r
+ //\r
+ // Disable early BRESP - use to optimise CLCD performance\r
+ DmcWriteReg(DMC_FEATURE_CRTL_REG, 0x00000001);\r
+ }\r
+\r
+ //\r
+ // Config memories\r
+ //\r
+ for (Chip = 0; Chip < DmcConfig->MaxChip; Chip++) {\r
+ // Send nop\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_NOP);\r
+\r
+ // Pre-charge all\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);\r
+\r
+ // Delay\r
+ for (Index = 0; Index < 10; Index++) {\r
+ DmcReadReg(DMC_STATUS_REG);\r
+ }\r
+\r
+ // Set (EMR2) extended mode register 2\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG,\r
+ DMC_DIRECT_CMD_CHIP_ADDR(Chip) |\r
+ DMC_DIRECT_CMD_BANKADDR(2) |\r
+ DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
+\r
+ // Set (EMR3) extended mode register 3\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG,\r
+ DMC_DIRECT_CMD_CHIP_ADDR(Chip) |\r
+ DMC_DIRECT_CMD_BANKADDR(3) |\r
+ DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
+\r
+ //\r
+ // Set (EMR) Extended Mode Register\r
+ //\r
+ // Put into OCD default state\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG,DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_BANKADDR(1) | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
+\r
+ //\r
+ // Set (MR) mode register - With DLL reset\r
+ //\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG | DmcConfig->ModeReg | DDR2_MR_DLL_RESET);\r
+\r
+ // Pre-charge all\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);\r
+ // Auto-refresh\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);\r
+ // Auto-refresh\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);\r
+\r
+ //\r
+ // Set (MR) mode register - Without DLL reset\r
+ //\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG | DmcConfig->ModeReg);\r
+\r
+ // Delay\r
+ for (Index = 0; Index < 10; Index++) {\r
+ DmcReadReg(DMC_STATUS_REG);\r
+ }\r
+\r
+ //\r
+ // Set (EMR) extended mode register - Enable OCD defaults\r
+ //\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | (0x00090000) |\r
+ (1 << DDR_MODESET_SHFT) | (DDR_EMR_OCD_DEFAULT << DDR_EMR_OCD_SHIFT) | DmcConfig->ExtModeReg);\r
+\r
+ // Delay\r
+ for (Index = 0; Index < 10; Index++) {\r
+ DmcReadReg(DMC_STATUS_REG);\r
+ }\r
+\r
+ // Set (EMR) extended mode register - OCD Exit\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | (0x00090000) |\r
+ (1 << DDR_MODESET_SHFT) | (DDR_EMR_OCD_NS << DDR_EMR_OCD_SHIFT) | DmcConfig->ExtModeReg);\r
+ }\r
+\r
+ // Move DDR2 Controller to Ready state by issueing GO command\r
+ DmcWriteReg(DMC_COMMAND_REG, DMC_COMMAND_GO);\r
+\r
+ // wait for ready\r
+ while (!(DmcReadReg(DMC_STATUS_REG) & DMC_STATUS_READY));\r
+\r
+}\r
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