--- /dev/null
+/** @file\r
+\r
+ This header file contains the platform independent parts of ARM Mali DP\r
+\r
+ Copyright (c) 2017-2018, Arm Limited. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+#ifndef ARMMALIDP_H_\r
+#define ARMMALIDP_H_\r
+\r
+#define DP_BASE (FixedPcdGet64 (PcdArmMaliDpBase))\r
+\r
+// MALI DP Ids\r
+#define MALIDP_NOT_PRESENT 0xFFF\r
+#define MALIDP_500 0x500\r
+#define MALIDP_550 0x550\r
+#define MALIDP_650 0x650\r
+\r
+// DP500 Peripheral Ids\r
+#define DP500_ID_PART_0 0x00\r
+#define DP500_ID_DES_0 0xB\r
+#define DP500_ID_PART_1 0x5\r
+\r
+#define DP500_ID_REVISION 0x1\r
+#define DP500_ID_JEDEC 0x1\r
+#define DP500_ID_DES_1 0x3\r
+\r
+#define DP500_PERIPHERAL_ID0_VAL (DP500_ID_PART_0)\r
+#define DP500_PERIPHERAL_ID1_VAL ((DP500_ID_DES_0 << 4) \\r
+ | DP500_ID_PART_1)\r
+#define DP500_PERIPHERAL_ID2_VAL ((DP500_ID_REVISION << 4) \\r
+ | (DP500_ID_JEDEC << 3) \\r
+ | (DP500_ID_DES_1))\r
+\r
+// DP550 Peripheral Ids\r
+#define DP550_ID_PART_0 0x50\r
+#define DP550_ID_DES_0 0xB\r
+#define DP550_ID_PART_1 0x5\r
+\r
+#define DP550_ID_REVISION 0x0\r
+#define DP550_ID_JEDEC 0x1\r
+#define DP550_ID_DES_1 0x3\r
+\r
+#define DP550_PERIPHERAL_ID0_VAL (DP550_ID_PART_0)\r
+#define DP550_PERIPHERAL_ID1_VAL ((DP550_ID_DES_0 << 4) \\r
+ | DP550_ID_PART_1)\r
+#define DP550_PERIPHERAL_ID2_VAL ((DP550_ID_REVISION << 4) \\r
+ | (DP550_ID_JEDEC << 3) \\r
+ | (DP550_ID_DES_1))\r
+\r
+// DP650 Peripheral Ids\r
+#define DP650_ID_PART_0 0x50\r
+#define DP650_ID_DES_0 0xB\r
+#define DP650_ID_PART_1 0x6\r
+\r
+#define DP650_ID_REVISION 0x0\r
+#define DP650_ID_JEDEC 0x1\r
+#define DP650_ID_DES_1 0x3\r
+\r
+#define DP650_PERIPHERAL_ID0_VAL (DP650_ID_PART_0)\r
+#define DP650_PERIPHERAL_ID1_VAL ((DP650_ID_DES_0 << 4) \\r
+ | DP650_ID_PART_1)\r
+#define DP650_PERIPHERAL_ID2_VAL ((DP650_ID_REVISION << 4) \\r
+ | (DP650_ID_JEDEC << 3) \\r
+ | (DP650_ID_DES_1))\r
+\r
+// Display Engine (DE) control register offsets for DP550/DP650\r
+#define DP_DE_STATUS 0x00000\r
+#define DP_DE_IRQ_SET 0x00004\r
+#define DP_DE_IRQ_MASK 0x00008\r
+#define DP_DE_IRQ_CLEAR 0x0000C\r
+#define DP_DE_CONTROL 0x00010\r
+#define DP_DE_PROG_LINE 0x00014\r
+#define DP_DE_AXI_CONTROL 0x00018\r
+#define DP_DE_AXI_QOS 0x0001C\r
+#define DP_DE_DISPLAY_FUNCTION 0x00020\r
+\r
+#define DP_DE_H_INTERVALS 0x00030\r
+#define DP_DE_V_INTERVALS 0x00034\r
+#define DP_DE_SYNC_CONTROL 0x00038\r
+#define DP_DE_HV_ACTIVESIZE 0x0003C\r
+#define DP_DE_DISPLAY_SIDEBAND 0x00040\r
+#define DP_DE_BACKGROUND_COLOR 0x00044\r
+#define DP_DE_DISPLAY_SPLIT 0x00048\r
+#define DP_DE_OUTPUT_DEPTH 0x0004C\r
+\r
+// Display Engine (DE) control register offsets for DP500\r
+#define DP_DE_DP500_CORE_ID 0x00018\r
+#define DP_DE_DP500_CONTROL 0x0000C\r
+#define DP_DE_DP500_PROG_LINE 0x00010\r
+#define DP_DE_DP500_H_INTERVALS 0x00028\r
+#define DP_DE_DP500_V_INTERVALS 0x0002C\r
+#define DP_DE_DP500_SYNC_CONTROL 0x00030\r
+#define DP_DE_DP500_HV_ACTIVESIZE 0x00034\r
+#define DP_DE_DP500_BG_COLOR_RG 0x0003C\r
+#define DP_DE_DP500_BG_COLOR_B 0x00040\r
+\r
+/* Display Engine (DE) graphics layer (LG) register offsets\r
+ * NOTE: For DP500 it will be LG2.\r
+ */\r
+#define DE_LG_OFFSET 0x00300\r
+#define DP_DE_LG_FORMAT (DE_LG_OFFSET)\r
+#define DP_DE_LG_CONTROL (DE_LG_OFFSET + 0x04)\r
+#define DP_DE_LG_COMPOSE (DE_LG_OFFSET + 0x08)\r
+#define DP_DE_LG_IN_SIZE (DE_LG_OFFSET + 0x0C)\r
+#define DP_DE_LG_CMP_SIZE (DE_LG_OFFSET + 0x10)\r
+#define DP_DE_LG_OFFSET (DE_LG_OFFSET + 0x14)\r
+#define DP_DE_LG_H_STRIDE (DE_LG_OFFSET + 0x18)\r
+#define DP_DE_LG_PTR_LOW (DE_LG_OFFSET + 0x1C)\r
+#define DP_DE_LG_PTR_HIGH (DE_LG_OFFSET + 0x20)\r
+#define DP_DE_LG_CHROMA_KEY (DE_LG_OFFSET + 0x2C)\r
+#define DP_DE_LG_AD_CONTROL (DE_LG_OFFSET + 0x30)\r
+#define DP_DE_LG_MMU_CONTROL (DE_LG_OFFSET + 0x48)\r
+\r
+// Display core (DC) control register offsets.\r
+#define DP_DC_OFFSET 0x0C000\r
+#define DP_DC_STATUS (DP_DC_OFFSET + 0x00)\r
+#define DP_DC_IRQ_SET (DP_DC_OFFSET + 0x04)\r
+#define DP_DC_IRQ_MASK (DP_DC_OFFSET + 0x08)\r
+#define DP_DC_IRQ_CLEAR (DP_DC_OFFSET + 0x0C)\r
+#define DP_DC_CONTROL (DP_DC_OFFSET + 0x10)\r
+#define DP_DC_CONFIG_VALID (DP_DC_OFFSET + 0x14)\r
+#define DP_DC_CORE_ID (DP_DC_OFFSET + 0x18)\r
+\r
+// DP500 has a global configuration register.\r
+#define DP_DP500_CONFIG_VALID (0xF00)\r
+\r
+// Display core ID register offsets.\r
+#define DP_DC_ID_OFFSET 0x0FF00\r
+#define DP_DC_ID_PERIPHERAL_ID4 (DP_DC_ID_OFFSET + 0xD0)\r
+#define DP_DC_CONFIGURATION_ID (DP_DC_ID_OFFSET + 0xD4)\r
+#define DP_DC_PERIPHERAL_ID0 (DP_DC_ID_OFFSET + 0xE0)\r
+#define DP_DC_PERIPHERAL_ID1 (DP_DC_ID_OFFSET + 0xE4)\r
+#define DP_DC_PERIPHERAL_ID2 (DP_DC_ID_OFFSET + 0xE8)\r
+#define DP_DC_COMPONENT_ID0 (DP_DC_ID_OFFSET + 0xF0)\r
+#define DP_DC_COMPONENT_ID1 (DP_DC_ID_OFFSET + 0xF4)\r
+#define DP_DC_COMPONENT_ID2 (DP_DC_ID_OFFSET + 0xF8)\r
+#define DP_DC_COMPONENT_ID3 (DP_DC_ID_OFFSET + 0xFC)\r
+\r
+#define DP_DP500_ID_OFFSET 0x0F00\r
+#define DP_DP500_ID_PERIPHERAL_ID4 (DP_DP500_ID_OFFSET + 0xD0)\r
+#define DP_DP500_CONFIGURATION_ID (DP_DP500_ID_OFFSET + 0xD4)\r
+#define DP_DP500_PERIPHERAL_ID0 (DP_DP500_ID_OFFSET + 0xE0)\r
+#define DP_DP500_PERIPHERAL_ID1 (DP_DP500_ID_OFFSET + 0xE4)\r
+#define DP_DP500_PERIPHERAL_ID2 (DP_DP500_ID_OFFSET + 0xE8)\r
+#define DP_DP500_COMPONENT_ID0 (DP_DP500_ID_OFFSET + 0xF0)\r
+#define DP_DP500_COMPONENT_ID1 (DP_DP500_ID_OFFSET + 0xF4)\r
+#define DP_DP500_COMPONENT_ID2 (DP_DP500_ID_OFFSET + 0xF8)\r
+#define DP_DP500_COMPONENT_ID3 (DP_DP500_ID_OFFSET + 0xFC)\r
+\r
+// Display status configuration mode activation flag\r
+#define DP_DC_STATUS_CM_ACTIVE_FLAG (0x1U << 16)\r
+\r
+// Display core control configuration mode\r
+#define DP_DC_CONTROL_SRST_ACTIVE (0x1U << 18)\r
+#define DP_DC_CONTROL_CRST_ACTIVE (0x1U << 17)\r
+#define DP_DC_CONTROL_CM_ACTIVE (0x1U << 16)\r
+\r
+#define DP_DE_DP500_CONTROL_SOFTRESET_REQ (0x1U << 16)\r
+#define DP_DE_DP500_CONTROL_CONFIG_REQ (0x1U << 17)\r
+\r
+// Display core configuration valid register\r
+#define DP_DC_CONFIG_VALID_CVAL (0x1U)\r
+\r
+// DC_CORE_ID\r
+// Display core version register PRODUCT_ID\r
+#define DP_DC_CORE_ID_SHIFT 16\r
+#define DP_DE_DP500_CORE_ID_SHIFT DP_DC_CORE_ID_SHIFT\r
+\r
+// Timing settings\r
+#define DP_DE_HBACKPORCH_SHIFT 16\r
+#define DP_DE_VBACKPORCH_SHIFT 16\r
+#define DP_DE_VSP_SHIFT 28\r
+#define DP_DE_VSYNCWIDTH_SHIFT 16\r
+#define DP_DE_HSP_SHIFT 13\r
+#define DP_DE_V_ACTIVE_SHIFT 16\r
+\r
+// BACKGROUND_COLOR\r
+#define DP_DE_BG_R_PIXEL_SHIFT 16\r
+#define DP_DE_BG_G_PIXEL_SHIFT 8\r
+\r
+//Graphics layer LG_FORMAT Pixel Format\r
+#define DP_PIXEL_FORMAT_ARGB_8888 0x8\r
+#define DP_PIXEL_FORMAT_ABGR_8888 0x9\r
+#define DP_PIXEL_FORMAT_RGBA_8888 0xA\r
+#define DP_PIXEL_FORMAT_BGRA_8888 0xB\r
+#define DP_PIXEL_FORMAT_XRGB_8888 0x10\r
+#define DP_PIXEL_FORMAT_XBGR_8888 0x11\r
+#define DP_PIXEL_FORMAT_RGBX_8888 0x12\r
+#define DP_PIXEL_FORMAT_BGRX_8888 0x13\r
+#define DP_PIXEL_FORMAT_RGB_888 0x18\r
+#define DP_PIXEL_FORMAT_BGR_888 0x19\r
+\r
+// DP500 format code are different than DP550/DP650\r
+#define DP_PIXEL_FORMAT_DP500_ARGB_8888 0x2\r
+#define DP_PIXEL_FORMAT_DP500_ABGR_8888 0x3\r
+#define DP_PIXEL_FORMAT_DP500_XRGB_8888 0x4\r
+#define DP_PIXEL_FORMAT_DP500_XBGR_8888 0x5\r
+\r
+// Graphics layer LG_PTR_LOW and LG_PTR_HIGH\r
+#define DP_DE_LG_PTR_LOW_MASK 0xFFFFFFFFU\r
+#define DP_DE_LG_PTR_HIGH_SHIFT 32\r
+\r
+// Graphics layer LG_CONTROL register characteristics\r
+#define DP_DE_LG_L_ALPHA_SHIFT 16\r
+#define DP_DE_LG_CHK_SHIFT 15\r
+#define DP_DE_LG_PMUL_SHIFT 14\r
+#define DP_DE_LG_COM_SHIFT 12\r
+#define DP_DE_LG_VFP_SHIFT 11\r
+#define DP_DE_LG_HFP_SHIFT 10\r
+#define DP_DE_LG_ROTATION_SHIFT 8\r
+\r
+#define DP_DE_LG_LAYER_BLEND_NO_BG 0x0U\r
+#define DP_DE_LG_PIXEL_BLEND_NO_BG 0x1U\r
+#define DP_DE_LG_LAYER_BLEND_BG 0x2U\r
+#define DP_DE_LG_PIXEL_BLEND_BG 0x3U\r
+#define DP_DE_LG_ENABLE 0x1U\r
+\r
+// Graphics layer LG_IN_SIZE register characteristics\r
+#define DP_DE_LG_V_IN_SIZE_SHIFT 16\r
+\r
+// Graphics layer LG_CMP_SIZE register characteristics\r
+#define DP_DE_LG_V_CMP_SIZE_SHIFT 16\r
+#define DP_DE_LG_V_OFFSET_SHIFT 16\r
+\r
+// Helper display timing macro functions.\r
+#define H_INTERVALS(Hfp, Hbp) ((Hbp << DP_DE_HBACKPORCH_SHIFT) | Hfp)\r
+#define V_INTERVALS(Vfp, Vbp) ((Vbp << DP_DE_VBACKPORCH_SHIFT) | Vfp)\r
+#define SYNC_WIDTH(Hsw, Vsw) ((Vsw << DP_DE_VSYNCWIDTH_SHIFT) | Hsw)\r
+#define HV_ACTIVE(Hor, Ver) ((Ver << DP_DE_V_ACTIVE_SHIFT) | Hor)\r
+\r
+// Helper layer graphics macros.\r
+#define FRAME_IN_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_IN_SIZE_SHIFT) | Hor)\r
+#define FRAME_CMP_SIZE(Hor, Ver) ((Ver << DP_DE_LG_V_CMP_SIZE_SHIFT) | Hor)\r
+\r
+#endif /* ARMMALIDP_H_ */\r
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