IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r
)\r
{\r
- // Data Cache enabled on Primary core when MMU is enabled.\r
- ArmDisableDataCache ();\r
- // Invalidate instruction cache\r
- ArmInvalidateInstructionCache ();\r
- // Enable Instruction Caches on all cores.\r
- ArmEnableInstructionCache ();\r
-\r
- InvalidateDataCacheRange (\r
- (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),\r
- PcdGet32 (PcdCPUCorePrimaryStackSize)\r
- );\r
+ if (!ArmMmuEnabled ()) {\r
+ // Data Cache enabled on Primary core when MMU is enabled.\r
+ ArmDisableDataCache ();\r
+ // Invalidate instruction cache\r
+ ArmInvalidateInstructionCache ();\r
+ // Enable Instruction Caches on all cores.\r
+ ArmEnableInstructionCache ();\r
+\r
+ InvalidateDataCacheRange (\r
+ (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),\r
+ PcdGet32 (PcdCPUCorePrimaryStackSize)\r
+ );\r
+ }\r
\r
//\r
// Note: Doesn't have to Enable CPU interface in non-secure world,\r