ArmPlatformPkg/PrePeiCore: permit entry with the MMU enabled

Some platforms may set up a preliminary ID map in flash and enter EFI
with the MMU and caches enabled, as this removes a lot of the complexity
around cache coherency. Let's take this into account, and avoid touching
the MMU controls or perform cache invalidation when the MMU is enabled
at entry.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>

diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
index 9c4b25df953dc371084790e468fda3371cbeb44b..8b86c6e69abdde98a0f58de07dd8812abad5f250 100644 (file)
--- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
+++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c
@@ -58,17 +58,19 @@ CEntryPoint (
   IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint\r
   )\r
 {\r
-  // Data Cache enabled on Primary core when MMU is enabled.\r
-  ArmDisableDataCache ();\r
-  // Invalidate instruction cache\r
-  ArmInvalidateInstructionCache ();\r
-  // Enable Instruction Caches on all cores.\r
-  ArmEnableInstructionCache ();\r
-\r
-  InvalidateDataCacheRange (\r
-    (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),\r
-    PcdGet32 (PcdCPUCorePrimaryStackSize)\r
-    );\r
+  if (!ArmMmuEnabled ()) {\r
+    // Data Cache enabled on Primary core when MMU is enabled.\r
+    ArmDisableDataCache ();\r
+    // Invalidate instruction cache\r
+    ArmInvalidateInstructionCache ();\r
+    // Enable Instruction Caches on all cores.\r
+    ArmEnableInstructionCache ();\r
+\r
+    InvalidateDataCacheRange (\r
+      (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),\r
+      PcdGet32 (PcdCPUCorePrimaryStackSize)\r
+      );\r
+  }\r
 \r
   //\r
   // Note: Doesn't have to Enable CPU interface in non-secure world,\r